From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMWgX-0006SP-Kd for qemu-devel@nongnu.org; Tue, 04 Aug 2015 03:30:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZMWgS-0004qJ-1q for qemu-devel@nongnu.org; Tue, 04 Aug 2015 03:30:53 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:34247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMWgR-0004pq-KK for qemu-devel@nongnu.org; Tue, 04 Aug 2015 03:30:47 -0400 Received: by wibud3 with SMTP id ud3so164537083wib.1 for ; Tue, 04 Aug 2015 00:30:46 -0700 (PDT) References: <1438358041-18021-1-git-send-email-alex.bennee@linaro.org> <1438358041-18021-12-git-send-email-alex.bennee@linaro.org> <87oaioll54.fsf@linaro.org> <87mvy8l5kt.fsf@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Tue, 04 Aug 2015 08:30:43 +0100 Message-ID: <87lhdrldcs.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v5 11/11] new: arm/barrier-test for memory barriers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: alvise rigo Cc: mttcg@listserver.greensocs.com, Peter Maydell , Andrew Jones , Claudio Fontana , kvm@vger.kernel.org, Alexander Spyridakis , Mark Burton , QEMU Developers , KONRAD =?utf-8?B?RnLDqWTDqXJpYw==?= alvise rigo writes: > On Mon, Aug 3, 2015 at 6:06 PM, Alex Bennée wrote: > >> >> alvise rigo writes: >> >> > On Mon, Aug 3, 2015 at 12:30 PM, Alex Bennée >> wrote: >> >> >> >> alvise rigo writes: >> >> >> >>> Hi Alex, >> >>> >> >>> Nice set of tests, they are proving to be helpful. >> >>> One question below. >> >>> >> >> >>> >> >>> Why are we calling these last two instructions with the 'eq' suffix? >> >>> Shouldn't we just strex r1, r0, [sptr] and then cmp r1, #0? >> >> >> >> Possibly, my armv7 is a little rusty. I'm just looking at tweaking this >> >> test now so I'll try and clean that up. >> >> Please find the updated test attached. I've also included some new test >> modes. In theory the barrier test by itself should still fail but it >> > > Thanks, I will check them out. > > >> passes on real ARMv7 as well as TCG. I'm trying to run the test on a >> heavier core-ed ARMv7 to check. I suspect we get away with it on >> ARMv7-on-x86_64 due to the strong ordering of the x86. > > >> The "excl" and "acqrel" tests now run without issue (although again >> plain acqrel semantics shouldn't stop a race corrupting shared_value). > > > > I suppose that, in order to have some race conditions due to a lack of a > proper emulation of barriers and acqrel instructions, we need a test that > does not involve atomic instructions at all, to reduce the emulation > overhead as much as possible. > Does this sound reasonable? I'm writing a "lockless" test now which uses just barriers and a postbox style signal. But as I say I need to understand why the pure "barrier" tests still works when it really shouldn't. > > >> >> I'll tweak the v8 versions of the test tomorrow. >> >> -- >> Alex Bennée >> >> -- Alex Bennée