From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44589) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrlrt-0000B8-D5 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:23:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrlrn-0006tg-Uz for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:22:57 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:46193 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrlrn-0006tN-P2 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:22:51 -0400 References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-7-git-send-email-edgar.iglesias@gmail.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1401434911-26992-7-git-send-email-edgar.iglesias@gmail.com> Date: Tue, 03 Jun 2014 11:22:51 +0100 Message-ID: <87lhtes35w.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v1 06/16] target-arm: Add FAR_EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, christoffer.dall@linaro.org, rth@twiddle.net Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 2 +- > target-arm/helper.c | 6 ++++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index f8ca1da..ef6a95d 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -187,7 +187,7 @@ typedef struct CPUARMState { > uint32_t ifsr_el2; /* Fault status registers. */ > uint64_t esr_el[4]; > uint32_t c6_region[8]; /* MPU base/size registers. */ > - uint64_t far_el[2]; /* Fault address registers. */ > + uint64_t far_el[4]; /* Fault address registers. */ Ahh my confusion from earlier is now clear. Perhaps the two commits should be merged? > uint64_t par_el1; /* Translation result. */ > uint32_t c9_insn; /* Cache lockdown registers. */ > uint32_t c9_data; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index da210b9..de5ee40 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 1, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 1, > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, > + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, > { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, -- Alex Bennée