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Fri, 12 Dec 2025 18:10:47 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id q6WEFadaPGkEEAAAD6G6ig (envelope-from ); Fri, 12 Dec 2025 18:10:47 +0000 From: Fabiano Rosas To: Tao Tang , Paolo Bonzini , Laurent Vivier , Eric Auger , Peter Maydell , Alex =?utf-8?Q?Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , CLEMENT MATHIEU--DRIF , Tao Tang Subject: Re: [RFC v6 4/4] tests/qtest: Add SMMUv3 bare-metal test using iommu-testdev In-Reply-To: <20251206155203.3015881-5-tangtao1634@phytium.com.cn> References: <20251206155203.3015881-1-tangtao1634@phytium.com.cn> <20251206155203.3015881-5-tangtao1634@phytium.com.cn> Date: Fri, 12 Dec 2025 15:10:44 -0300 Message-ID: <87ms3nvae3.fsf@suse.de> MIME-Version: 1.0 Content-Type: text/plain X-Spamd-Result: default: False [-4.30 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-0.995]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; MISSING_XM_UA(0.00)[]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_TLS_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_TWELVE(0.00)[15]; FROM_EQ_ENVFROM(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_DN_SOME(0.00)[] Received-SPF: pass client-ip=2a07:de40:b251:101:10:150:64:2; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Tao Tang writes: > Add a qtest suite that validates ARM SMMUv3 translation without guest > firmware or OS. The tests leverage iommu-testdev to trigger DMA > operations and the qos-smmuv3 library to configure IOMMU translation > structures. > > This test suite targets the virt machine and covers: > - Stage 1 only translation (VA -> PA via CD page tables) > - Stage 2 only translation (IPA -> PA via STE S2 tables) > - Nested translation (VA -> IPA -> PA, Stage 1 + Stage 2) > - Design to extended to support multiple security spaces > (Non-Secure, Secure, Root, Realm) > > Each test case follows this sequence: > 1. Initialize SMMUv3 with appropriate command/event queues > 2. Build translation tables (STE/CD/PTE) for the target scenario > 3. Configure iommu-testdev with IOVA and DMA attributes via MMIO > 4. Trigger DMA and validate successful translation > 5. Verify data integrity through a deterministic write-read pattern > > This bare-metal approach provides deterministic IOMMU testing with > minimal dependencies, making failures directly attributable to the SMMU > translation path. > > Signed-off-by: Tao Tang > Tested-by: Pierrick Bouvier > Reviewed-by: Pierrick Bouvier > --- > tests/qtest/iommu-smmuv3-test.c | 131 ++++++++++++++++++++++++++++++++ > tests/qtest/meson.build | 1 + > 2 files changed, 132 insertions(+) > create mode 100644 tests/qtest/iommu-smmuv3-test.c > > diff --git a/tests/qtest/iommu-smmuv3-test.c b/tests/qtest/iommu-smmuv3-test.c > new file mode 100644 > index 0000000000..96f66ee325 > --- /dev/null > +++ b/tests/qtest/iommu-smmuv3-test.c > @@ -0,0 +1,131 @@ > +/* > + * QTest for SMMUv3 with iommu-testdev > + * > + * This QTest file is used to test the SMMUv3 with iommu-testdev so that we can > + * test SMMUv3 without any guest kernel or firmware. > + * > + * Copyright (c) 2025 Phytium Technology > + * > + * Author: > + * Tao Tang > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest.h" > +#include "libqos/pci.h" > +#include "libqos/generic-pcihost.h" > +#include "hw/pci/pci_regs.h" > +#include "hw/misc/iommu-testdev.h" > +#include "libqos/qos-smmuv3.h" > + > +#define DMA_LEN 4 > + > +static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QGenericPCIBus *gbus, > + QPCIBar *bar) > +{ > + uint16_t vid, did; > + QPCIDevice *dev = NULL; > + > + qpci_init_generic(gbus, qts, NULL, false); > + > + /* Find device by vendor/device ID to avoid slot surprises. */ > + for (int s = 0; s < 32 && !dev; s++) { > + for (int fn = 0; fn < 8 && !dev; fn++) { > + QPCIDevice *cand = qpci_device_find(&gbus->bus, QPCI_DEVFN(s, fn)); > + if (!cand) { > + continue; > + } > + vid = qpci_config_readw(cand, PCI_VENDOR_ID); > + did = qpci_config_readw(cand, PCI_DEVICE_ID); > + if (vid == IOMMU_TESTDEV_VENDOR_ID && > + did == IOMMU_TESTDEV_DEVICE_ID) { > + dev = cand; > + g_test_message("Found iommu-testdev! devfn: 0x%x", cand->devfn); > + } else { > + g_free(cand); > + } > + } > + } This loop could be replaced with something simpler: static void save_fn(QPCIDevice *dev, int devfn, void *data) { QPCIDevice **pdev = (QPCIDevice **) data; *pdev = dev; } qpci_device_foreach(&gbus->bus, IOMMU_TESTDEV_VENDOR_ID, IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev); > + g_assert(dev); > + > + qpci_device_enable(dev); > + *bar = qpci_iomap(dev, 0, NULL); > + g_assert_false(bar->is_io); > + > + return dev; > +} > + > +static void run_smmuv3_translation(const QSMMUTestConfig *cfg) > +{ > + QTestState *qts; > + QGenericPCIBus gbus; > + QPCIDevice *dev; > + QPCIBar bar; > + > + /* Initialize QEMU environment for SMMU testing */ > + qts = qtest_init("-machine virt,acpi=off,gic-version=3,iommu=smmuv3 " > + "-smp 1 -m 512 -cpu max -net none " > + "-device iommu-testdev"); > + > + /* Setup and configure PCI device */ > + dev = setup_qtest_pci_device(qts, &gbus, &bar); > + g_assert(dev); > + > + g_test_message("### SMMUv3 translation mode=%d sec_sid=%d ###", > + cfg->trans_mode, cfg->sec_sid); > + qsmmu_run_translation_case(qts, dev, bar, VIRT_SMMU_BASE, cfg); > + qtest_quit(qts); > +} > + > +static void test_smmuv3_ns_s1_only(void) > +{ > + QSMMUTestConfig cfg = { > + .trans_mode = QSMMU_TM_S1_ONLY, > + .sec_sid = QSMMU_SEC_SID_NONSECURE, > + .dma_iova = QSMMU_IOVA_OR_IPA, > + .dma_len = DMA_LEN, > + .expected_result = 0, > + }; > + > + run_smmuv3_translation(&cfg); > +} > + > +static void test_smmuv3_ns_s2_only(void) > +{ > + QSMMUTestConfig cfg = { > + .trans_mode = QSMMU_TM_S2_ONLY, > + .sec_sid = QSMMU_SEC_SID_NONSECURE, > + .dma_iova = QSMMU_IOVA_OR_IPA, > + .dma_len = DMA_LEN, > + .expected_result = 0, > + }; > + > + run_smmuv3_translation(&cfg); > +} > + > +static void test_smmuv3_ns_nested(void) > +{ > + QSMMUTestConfig cfg = { > + .trans_mode = QSMMU_TM_NESTED, > + .sec_sid = QSMMU_SEC_SID_NONSECURE, > + .dma_iova = QSMMU_IOVA_OR_IPA, > + .dma_len = DMA_LEN, > + .expected_result = 0, > + }; > + > + run_smmuv3_translation(&cfg); > +} > + > +int main(int argc, char **argv) > +{ > + g_test_init(&argc, &argv, NULL); > + qtest_add_func("/iommu-testdev/translation/ns-s1-only", > + test_smmuv3_ns_s1_only); > + qtest_add_func("/iommu-testdev/translation/ns-s2-only", > + test_smmuv3_ns_s2_only); > + qtest_add_func("/iommu-testdev/translation/ns-nested", > + test_smmuv3_ns_nested); > + return g_test_run(); > +} > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 669d07c06b..e2d2e68092 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -263,6 +263,7 @@ qtests_aarch64 = \ > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ > (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ > + (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-smmuv3-test'] : []) + \ > qtests_cxl + \ > ['arm-cpu-features', > 'numa-test',