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Wed, 17 Jan 2024 13:46:04 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Michael Tokarev Cc: Richard Henderson , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , QEMU Developers , qemu-s390x , David Hildenbrand Subject: Re: chacha20-s390 broken in 8.2.0 in TCG on s390x In-Reply-To: (Michael Tokarev's message of "Wed, 17 Jan 2024 14:53:35 +0300") References: <764215cd-6f62-4746-b1f5-6174a158f95d@linaro.org> <5c3098cc-3a2f-4272-b06a-6d12d645d628@linaro.org> User-Agent: mu4e 1.11.27; emacs 29.1 Date: Wed, 17 Jan 2024 13:46:04 +0000 Message-ID: <87mst4hy3n.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Michael Tokarev writes: > 04.01.2024 01:51, Richard Henderson : >> On 1/4/24 01:37, Philippe Mathieu-Daud=C3=A9 wrote: >>> Finally changing the constraints on op_rotli_vec seems to fix it: >>> >>> --- >>> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc >>> index fbee43d3b0..b3456fe857 100644 >>> --- a/tcg/s390x/tcg-target.c.inc >>> +++ b/tcg/s390x/tcg-target.c.inc >>> @@ -3264,13 +3264,13 @@ static TCGConstraintSetIndex tcg_target_op_def(= TCGOpcode op) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_ld_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_dupm_vec: >>> +=C2=A0=C2=A0=C2=A0 case INDEX_op_rotli_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return C_O1_I1(v= , r); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_dup_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return C_O1_I1(v= , vr); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_abs_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_neg_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_not_vec: >>> -=C2=A0=C2=A0=C2=A0 case INDEX_op_rotli_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_sari_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_shli_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_shri_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_s390_vuph_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case INDEX_op_s390_vupl_vec: >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return C_O1_I1(v= , v); >> Definitely not correct, since VERLL requires a vector input to be >> rotated. >>=20 >>> But I'm outside of my comfort zone so not really sure what I'm doing... >>> (I was inspired by the "the instruction verll only allows immediates up >>> to 32 bits." comment from >>> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg317099.html) >> That message is confused.=C2=A0 The immediate in VERLL is 12 bits (with >> only 6 bits ever used for MO_64).=C2=A0 Dunno where "32 bits" comes from. > > So, what do we have here in the end? > Should we fix this on qemu side? I think the thinking is we should disable the optimisation for the 8.2 stable while figuring out the true fix for 9.0. > > This thread stopped quite some time ago, with problematic > instruction found but no solution.. > > Thanks, > > /mjt --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro