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Thu, 01 Apr 2021 04:41:06 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j30sm10585803wrj.62.2021.04.01.04.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 04:41:05 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1AD2A1FF7E; Thu, 1 Apr 2021 12:41:05 +0100 (BST) References: <20210401100457.191458-1-kele.hwang@gmail.com> User-agent: mu4e 1.5.11; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Kele Huang Subject: Re: [1/1] tcg/mips: Fix SoftTLB comparison on mips backend Date: Thu, 01 Apr 2021 12:40:50 +0100 In-reply-to: <20210401100457.191458-1-kele.hwang@gmail.com> Message-ID: <87mtui1bce.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, f4bug@amsat.org, alistair.francis@wdc.com, j@getutm.app Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Kele Huang writes: > The addrl used to compare with SoftTLB entry should be sign-extended > in common case, and it will cause constant failing in SoftTLB > comparisons for the addrl whose address is over 0x80000000 on the > emulation of 32-bit guest on 64-bit host. > > This is an important performance bug fix. Spec2000 gzip rate increase > from ~45 to ~140 on Loongson 3A4000 (MIPS compatible platform). > > Signed-off-by: Kele Huang > --- > tcg/mips/tcg-target.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index 8738a3a581..8b16726242 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1201,13 +1201,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGRe= g base, TCGReg addrl, > load the tlb addend for the fast path. */ > tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); > } > - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); >=20=20 > /* Zero extend a 32-bit guest address for a 64-bit host. */ > if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { > tcg_out_ext32u(s, base, addrl); > addrl =3D base; > } > + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); >=20=20 > label_ptr[0] =3D s->code_ptr; > tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); Looks reasonable to me: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e