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X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , luis.machado@linaro.org, Sagar Karandikar , David Hildenbrand , Mark Cave-Ayland , qemu-devel@nongnu.org, Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , alan.hayward@arm.com, "open list:PowerPC TCG CPUs" , Aleksandar Rikalo , Richard Henderson , Philippe =?utf-8?Q?Mathieu?= =?utf-8?Q?-Daud=C3=A9?= , Artyom Tarasenko , Eduardo Habkost , richard.henderson@linaro.org, "open list:S390 TCG CPUs" , "open list:ARM TCG CPUs" , Stafford Horne , David Gibson , "open list:RISC-V TCG CPUs" , Bastian Koppelmann , Chris Wulff , Laurent Vivier , Michael Walle , Palmer Dabbelt , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Damien Hedde writes: > Hi Alex, > > On 12/11/19 6:05 PM, Alex Benn=C3=A9e wrote: >> Instead of passing a pointer to memory now just extend the GByteArray >> to all the read register helpers. They can then safely append their >> data through the normal way. We don't bother with this abstraction for >> write registers as we have already ensured the buffer being copied >> from is the correct size. >>=20 >> Signed-off-by: Alex Benn=C3=A9e > > [...] > >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 0ac950d6c71..6476245e789 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -47,30 +47,27 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, >>=20=20 >> static void switch_mode(CPUARMState *env, int mode); >>=20=20 >> -static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) >> +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) >> { >> int nregs; >>=20=20 >> /* VFP data registers are always little-endian. */ >> nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; >> if (reg < nregs) { >> - stq_le_p(buf, *aa32_vfp_dreg(env, reg)); >> - return 8; >> + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); > > It was a little-endian version, you've put a target-endian version. > Is that what you meant ? Yes - I suspect this would have been broken if used by a big-endian system. gdbstub generally (SVE excepted) wants things in target order. > >> } >> if (arm_feature(env, ARM_FEATURE_NEON)) { >> /* Aliases for Q regs. */ >> nregs +=3D 16; >> if (reg < nregs) { >> uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); >> - stq_le_p(buf, q[0]); >> - stq_le_p(buf + 8, q[1]); >> - return 16; >> + return gdb_get_reg128(buf, q[0], q[1]); > > Ditto here. > >> } >> } >> switch (reg - nregs) { >> - case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; >> - case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; >> - case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; >> + case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); b= reak; >> + case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; >> + case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); b= reak; >> } >> return 0; >> } >> @@ -101,7 +98,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t = *buf, int reg) >> return 0; >> } >>=20=20 >> -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int = reg) >> +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, i= nt reg) >> { >> switch (reg) { >> case 0 ... 31: >> @@ -204,7 +201,7 @@ static void write_raw_cp_reg(CPUARMState *env, const= ARMCPRegInfo *ri, >> } >> } >>=20=20 >> -static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) >> +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int re= g) >> { >> ARMCPU *cpu =3D env_archcpu(env); >> const ARMCPRegInfo *ri; > > [...] > >> diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c >> index 823759c92e7..6f08021cc22 100644 >> --- a/target/ppc/gdbstub.c >> +++ b/target/ppc/gdbstub.c >> @@ -114,10 +114,11 @@ void ppc_maybe_bswap_register(CPUPPCState *env, ui= nt8_t *mem_buf, int len) >> * the FP regs zero size when talking to a newer gdb. >> */ >>=20=20 >> -int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) >> +int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) >> { >> PowerPCCPU *cpu =3D POWERPC_CPU(cs); >> CPUPPCState *env =3D &cpu->env; >> + uint8_t *mem_buf; >> int r =3D ppc_gdb_register_len(n); >>=20=20 >> if (!r) { >> @@ -126,17 +127,17 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_= t *mem_buf, int n) >>=20=20 >> if (n < 32) { >> /* gprs */ >> - gdb_get_regl(mem_buf, env->gpr[n]); >> + gdb_get_regl(buf, env->gpr[n]); >> } else if (n < 64) { >> /* fprs */ >> - stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); >> + gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); >> } else { >> switch (n) { >> case 64: >> - gdb_get_regl(mem_buf, env->nip); >> + gdb_get_regl(buf, env->nip); >> break; >> case 65: >> - gdb_get_regl(mem_buf, env->msr); >> + gdb_get_regl(buf, env->msr); >> break; >> case 66: >> { >> @@ -145,31 +146,33 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_= t *mem_buf, int n) >> for (i =3D 0; i < 8; i++) { >> cr |=3D env->crf[i] << (32 - ((i + 1) * 4)); >> } >> - gdb_get_reg32(mem_buf, cr); >> + gdb_get_reg32(buf, cr); >> break; >> } >> case 67: >> - gdb_get_regl(mem_buf, env->lr); >> + gdb_get_regl(buf, env->lr); >> break; >> case 68: >> - gdb_get_regl(mem_buf, env->ctr); >> + gdb_get_regl(buf, env->ctr); >> break; >> case 69: >> - gdb_get_reg32(mem_buf, env->xer); >> + gdb_get_reg32(buf, env->xer); >> break; >> case 70: >> - gdb_get_reg32(mem_buf, env->fpscr); >> + gdb_get_reg32(buf, env->fpscr); >> break; >> } >> } >> + mem_buf =3D buf->data - r; > > Should it not be something more like this ? > mem_buf =3D buf->data + buf->len - r; Good catch. > > There seem to be the same issue below for every > ppc_maybe_bswap_register() call. Fixed. --=20 Alex Benn=C3=A9e