[Qemu-devel] [PATCH for 2.10] tcg: enable MTTCG by default for PPC64 on x86

[Qemu-devel] [PATCH for 2.10] tcg: enable MTTCG by default for PPC64 on x86

[Nikunj A Dadhania]

This enables the multi-threaded system emulation by default for PPC64
guests using the x86_64 TCG back-end.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---

Depends on following patch which fixes the define name:

https://patchwork.ozlabs.org/patch/748840/

---
 configure        | 2 ++
 target/ppc/cpu.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configure b/configure
index 4b3b5cd..2a87495 100755
--- a/configure
+++ b/configure
@@ -6008,12 +6008,14 @@ case "$target_name" in
   ppc64)
     TARGET_BASE_ARCH=ppc
     TARGET_ABI_DIR=ppc
+    mttcg=yes
     gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
   ;;
   ppc64le)
     TARGET_ARCH=ppc64
     TARGET_BASE_ARCH=ppc
     TARGET_ABI_DIR=ppc
+    mttcg=yes
     gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
   ;;
   ppc64abi32)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e0ff041..ece535d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -30,6 +30,8 @@
 #define TARGET_LONG_BITS 64
 #define TARGET_PAGE_BITS 12
 
+#define TCG_GUEST_DEFAULT_MO 0
+
 /* Note that the official physical address space bits is 62-M where M
    is implementation dependent.  I've not looked up M for the set of
    cpus we emulate at the system level.  */
-- 
2.9.3

Re: [Qemu-devel] [PATCH for 2.10] tcg: enable MTTCG by default for PPC64 on x86

[Alex Bennée]

Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> writes:

> This enables the multi-threaded system emulation by default for PPC64
> guests using the x86_64 TCG back-end.

Technically this enables it for all backends that can meet the guests
default memory model requirements. So far only the x86 backend defines
one as:

  #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)

>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>
> Depends on following patch which fixes the define name:
>
> https://patchwork.ozlabs.org/patch/748840/
>
> ---
>  configure        | 2 ++
>  target/ppc/cpu.h | 2 ++
>  2 files changed, 4 insertions(+)
>
> diff --git a/configure b/configure
> index 4b3b5cd..2a87495 100755
> --- a/configure
> +++ b/configure
> @@ -6008,12 +6008,14 @@ case "$target_name" in
>    ppc64)
>      TARGET_BASE_ARCH=ppc
>      TARGET_ABI_DIR=ppc
> +    mttcg=yes
>      gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
>    ;;
>    ppc64le)
>      TARGET_ARCH=ppc64
>      TARGET_BASE_ARCH=ppc
>      TARGET_ABI_DIR=ppc
> +    mttcg=yes
>      gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
>    ;;
>    ppc64abi32)
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index e0ff041..ece535d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -30,6 +30,8 @@
>  #define TARGET_LONG_BITS 64
>  #define TARGET_PAGE_BITS 12
>
> +#define TCG_GUEST_DEFAULT_MO 0
> +
>  /* Note that the official physical address space bits is 62-M where M
>     is implementation dependent.  I've not looked up M for the set of
>     cpus we emulate at the system level.  */


--
Alex Bennée

Re: [Qemu-devel] [PATCH for 2.10] tcg: enable MTTCG by default for PPC64 on x86

[David Gibson]

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On Mon, Apr 10, 2017 at 01:42:17PM +0530, Nikunj A Dadhania wrote:
> This enables the multi-threaded system emulation by default for PPC64
> guests using the x86_64 TCG back-end.
> 
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> 
> Depends on following patch which fixes the define name:
> 
> https://patchwork.ozlabs.org/patch/748840/

Applied to ppc-for-2.10.

> 
> ---
>  configure        | 2 ++
>  target/ppc/cpu.h | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/configure b/configure
> index 4b3b5cd..2a87495 100755
> --- a/configure
> +++ b/configure
> @@ -6008,12 +6008,14 @@ case "$target_name" in
>    ppc64)
>      TARGET_BASE_ARCH=ppc
>      TARGET_ABI_DIR=ppc
> +    mttcg=yes
>      gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
>    ;;
>    ppc64le)
>      TARGET_ARCH=ppc64
>      TARGET_BASE_ARCH=ppc
>      TARGET_ABI_DIR=ppc
> +    mttcg=yes
>      gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
>    ;;
>    ppc64abi32)
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index e0ff041..ece535d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -30,6 +30,8 @@
>  #define TARGET_LONG_BITS 64
>  #define TARGET_PAGE_BITS 12
>  
> +#define TCG_GUEST_DEFAULT_MO 0
> +
>  /* Note that the official physical address space bits is 62-M where M
>     is implementation dependent.  I've not looked up M for the set of
>     cpus we emulate at the system level.  */

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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