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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Sat, 15 Oct 2016 10:55:16 +0100
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Subject: Re: [Qemu-devel] [PATCH] target-arm/translate.c: fix movs pc,
 lr exception return on ARMv7
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>


Peter Maydell <peter.maydell@linaro.org> writes:

> On 14 October 2016 at 16:13, Alex Bennée <alex.bennee@linaro.org> wrote:
>> This was broken by the fix for 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0.
>> Specifically a movs pc,lr in the kernels ret_fast_syscall returning to
>> some thumb mode user space code but store_reg unconditionally aligned
>> the return PC instead of treating the return as an "interworking"
>> branch.
>>
>> I suspect we need to audit all calls to store_reg that might involve the
>> PC to ensure "interworking" branches are correctly handled. Also I'm not
>> quite sure how the code worked before 9b6a3e as the store_reg path
>> wouldn't have triggered the store_cpu_field(var, thumb) to set the
>> processor mode back to thumb.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> I think this is the wrong fix to the problem -- see the
> patch I sent a few days back.

Well at least my analysis of the problem was correct even if the
solution was too hacky. Your patch is obviously the better solution ;-)

For ref:

  [PATCH] Fix masking of PC lower bits when doing exception returns

>
> thanks
> -- PMM


--
Alex Bennée