Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table

["Alex Bennée" <alex.bennee@linaro.org>]

Shannon Zhao <zhaoshenglong@huawei.com> writes:

> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add PCIe controller in ACPI DSDT table, so the guest can detect
> the PCIe.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
>  hw/arm/virt-acpi-build.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index a979582..11574c9 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -48,6 +48,8 @@
>  #include "qapi/qmp/qint.h"
>  #include "qom/qom-qobject.h"
>  #include "exec/ram_addr.h"
> +#include "hw/pci/pcie_host.h"
> +#include "hw/pci/pci.h"
>  
>  /* #define DEBUG_ACPI_BUILD */
>  #ifdef DEBUG_ACPI_BUILD
> @@ -176,6 +178,143 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
>      }
>  }
>  
> +static void acpi_dsdt_add_pci(Aml *scope, acpi_pcie_info *info)
> +{
> +    Aml *dev, *rt_pkg, *pkg, *method, *rbuf, *crs;
> +    Aml *ifctx, *UUID, *ifctx1, *elsectx, *buf, *dev_rp0, *dev_gsi;
> +    int i, devfn;
> +    int irq = *info->pcie_irq + 32;
> +
> +    dev = aml_device("%s", "PCI0");
> +    aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> +    aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> +    aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> +    aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
> +    aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> +    aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
> +    aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
> +
> +    /* Declare the PCI Routing Table. */
> +    rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
> +    for (devfn = 0; devfn < info->nr_pcie_buses; devfn++) {
> +        for (i = 0; i < PCI_NUM_PINS; i++) {
> +            int gsi = (i + devfn) % PCI_NUM_PINS;
> +            pkg = aml_package(4);
> +            aml_append(pkg, aml_int((devfn << 16) | 0xFFFF));
> +            aml_append(pkg, aml_int(i));
> +            aml_append(pkg, aml_name("GSI%d", gsi));
> +            aml_append(pkg, aml_int(0));
> +            aml_append(rt_pkg, pkg);
> +        }
> +    }
> +    aml_append(dev, aml_name_decl("_PRT", rt_pkg));
> +
> +    for (i = 0; i < PCI_NUM_PINS; i++) {
> +        dev_gsi = aml_device("GSI%d", i);
> +        aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> +        aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
> +        crs = aml_resource_template();
> +        aml_append(crs, aml_interrupt(0x01, irq + i));
> +        aml_append(dev_gsi, aml_name_decl("_PRS", crs));
> +        crs = aml_resource_template();
> +        aml_append(crs, aml_interrupt(0x01, irq + i));
> +        aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> +        method = aml_method("_SRS", 1);
> +        aml_append(dev_gsi, method);
> +        aml_append(dev, dev_gsi);
> +    }
> +
> +    method = aml_method("_CBA", 0);
> +    aml_append(method, aml_return(aml_int(info->pcie_ecam_base)));
> +    aml_append(dev, method);
> +
> +    method = aml_method("_CRS", 0);
> +    rbuf = aml_resource_template();
> +    aml_append(rbuf,
> +        aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
> +                            0x0000, 0x0000, info->nr_pcie_buses - 1,
> +                            0x0000, info->nr_pcie_buses));
> +    aml_append(rbuf,
> +        aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
> +                         aml_cacheable, aml_ReadWrite,
> +                         0x0000, info->pcie_mmio_base,
> +                         info->pcie_mmio_base + info->pcie_mmio_size - 1,
> +                         0x0000, info->pcie_mmio_size));
> +    aml_append(rbuf,
> +        aml_dword_io(aml_min_fixed, aml_max_fixed,
> +                     aml_pos_decode, aml_entire_range,
> +                     0x0000, info->pcie_ioport_base,
> +                     info->pcie_ioport_base + info->pcie_ioport_size - 1,
> +                     0x0000, info->pcie_ioport_size));
> +
> +    aml_append(method, aml_name_decl("RBUF", rbuf));
> +    aml_append(method, aml_return(rbuf));
> +    aml_append(dev, method);
> +
> +    /* Declare an _OSC (OS Control Handoff) method */
> +    aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
> +    aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
> +    method = aml_method("_OSC", 4);
> +    aml_append(method,
> +        aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
> +
> +    UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
> 0x7441C03DD766);

This looks like a fairly unreadable uuid already. What are these magic numbers?

> +    ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> +    aml_append(ifctx,
> +        aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
> +    aml_append(ifctx,
> +        aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
> +    aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
> +    aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> +
> +    aml_append(ifctx, aml_and(aml_name("CTRL"),
> +        aml_int(0x1D), aml_name("CTRL")));
> +
> +    ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
> +    aml_append(ifctx1, aml_or(aml_name("CDW1"),
> +        aml_int(0x08), aml_name("CDW1")));
> +    aml_append(ifctx, ifctx1);
> +
> +    ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
> +    aml_append(ifctx1, aml_or(aml_name("CDW1"),
> +        aml_int(0x10), aml_name("CDW1")));
> +    aml_append(ifctx, ifctx1);
> +
> +    aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
> +    aml_append(ifctx, aml_return(aml_arg(3)));
> +
> +    aml_append(method, ifctx);
> +
> +    elsectx = aml_else();
> +    aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), aml_name("CDW1")));
> +    aml_append(elsectx, aml_return(aml_arg(3)));
> +    aml_append(method, elsectx);
> +
> +    aml_append(dev, method);
> +
> +    method = aml_method("_DSM", 4);
> +    UUID = aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117,
> 0xEA4D19C3434D);

Again lots of magic numbers.

> +    ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> +    ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> +    buf = aml_buffer();
> +    build_append_int_noprefix(buf->buf, 0x01, 1);
> +    aml_append(ifctx1, aml_return(buf));
> +    aml_append(ifctx, ifctx1);
> +    aml_append(method, ifctx);
> +
> +    buf = aml_buffer();
> +    build_append_int_noprefix(buf->buf, 0x00, 1);
> +    aml_append(method, aml_return(buf));
> +
> +    aml_append(dev, method);
> +
> +    dev_rp0 = aml_device("%s", "RP0");
> +    aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> +    aml_append(dev, dev_rp0);
> +
> +    aml_append(scope, dev);
> +}
> +
>  /* RSDP */
>  static GArray *
>  build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> @@ -358,6 +497,7 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>      acpi_dsdt_add_flash(scope, info->flash_addr);
>      acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
>               info->virtio_mmio_irq, info->virtio_mmio_num);
> +    acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>  
>      aml_append(dsdt, scope);
>      /* copy AML table into ACPI tables blob and patch header there */

-- 
Alex Bennée