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Thu, 08 May 2025 06:37:29 -0700 (PDT) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5fa7781b1d2sm11139496a12.39.2025.05.08.06.37.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 06:37:28 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 0A8E45F767; Thu, 8 May 2025 14:37:27 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-devel@nongnu.org, Julian Armistead , "open list:ARM TCG CPUs" Subject: Re: [RFC PATCH] target/arm: allow gdb to read ARM_CP_NORAW regs In-Reply-To: (Peter Maydell's message of "Thu, 8 May 2025 13:07:40 +0100") References: <20250507165840.401623-1-alex.bennee@linaro.org> <87zffnmidy.fsf@draig.linaro.org> User-Agent: mu4e 1.12.10; emacs 30.1 Date: Thu, 08 May 2025 14:37:26 +0100 Message-ID: <87o6w3mdex.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > On Thu, 8 May 2025 at 12:50, Alex Benn=C3=A9e wr= ote: >> >> Peter Maydell writes: >> >> > On Wed, 7 May 2025 at 17:58, Alex Benn=C3=A9e = wrote: >> >> >> >> Before this we suppress all ARM_CP_NORAW registers being listed under >> >> GDB. This includes useful registers like CurrentEL which gets tagged >> >> as ARM_CP_NO_RAW because it is one of the ARM_CP_SPECIAL_MASK >> >> registers. These are registers TCG can directly compute because we >> >> have the information at compile time but until now with no readfn. >> >> >> >> Add a .readfn to return the CurrentEL and then loosen the restrictions >> >> in arm_register_sysreg_for_feature to allow ARM_CP_NORAW registers to >> >> be read if there is a readfn available. >> > >> > The primary use case for NO_RAW is "system instructions" like >> > the TLB maintenance insns. These don't make sense to expose >> > to a debugger. >> >> I think we could re-think the logic: >> >> /* >> * By convention, for wildcarded registers only the first >> * entry is used for migration; the others are marked as >> * ALIAS so we don't try to transfer the register >> * multiple times. Special registers (ie NOP/WFI) are >> * never migratable and not even raw-accessible. >> */ >> if (r2->type & ARM_CP_SPECIAL_MASK) { >> r2->type |=3D ARM_CP_NO_RAW; >> } > > Well, we definitely don't want WFI or the DC ZVA etc > "registers" to be exposed to GDB or for us to try to handle > them in KVM state sync or migration... ARM_CP_NOP is less > clear because we use it pretty widely for more than one > purpose. The main one is "system instruction that we don't > need to implement". (CP_NOP + a readable register is a > questionable combination since the guest will expect it to > update the general-purpose destreg, not leave it untouched, > but we do have some.) > >> > If we want the gdbstub access to system registers to be >> > more than our current "we provide the ones that are easy", >> > then I think I'd like to see a bit more up-front analysis of >> > what the gdbstub needs and whether we've got into a bit of >> > a mess with our ARM_CP_* flags that we could straighten out. >> >> Yeah - hence the RFC. CurrentEL is a super useful one to expose though >> when you are debugging complex hypervisor setups. > > One problem with this patch is the one that the reporter of > https://gitlab.com/qemu-project/qemu/-/issues/2760 noted > in the conversation there: it will allow the debugger to > read registers which have a side-effect on read, like > ICC_IAR1_EL1: we almost certainly do not want to allow > the debugger to acknowledge an interrupt by doing a sysreg > read. Doesn't raw_readfn offer these semantics? /* * Function for doing a "raw" read; used when we need to copy * coprocessor state to the kernel for KVM or out for * migration. This only needs to be provided if there is also a * readfn and it has side effects (for instance clear-on-read bits). */ CPReadFn *raw_readfn; So maybe: /* We can only read ARM_CP_NO_RAW regs without side effects */ if ((ri->type & ARM_CP_NO_RAW) && !ri->raw_readfn) { return; } And I guess we can strengthen the gdb helper to NOP any writes to such registers. > > thanks > -- PMM --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro