From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B22A8CD1288 for ; Wed, 3 Apr 2024 06:33:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rruBH-000150-MO; Wed, 03 Apr 2024 02:33:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rruBG-00014Y-9Y for qemu-devel@nongnu.org; Wed, 03 Apr 2024 02:33:06 -0400 Received: from ik1-413-38519.vs.sakura.ne.jp ([153.127.30.23] helo=sakura.ysato.name) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rruBE-0008Vq-9j for qemu-devel@nongnu.org; Wed, 03 Apr 2024 02:33:06 -0400 Received: from SIOS1075.ysato.ml (fs9875fd8c.tkyc511.ap.nuro.jp [152.117.253.140]) by sakura.ysato.name (Postfix) with ESMTPSA id DA93E1C01EE; Wed, 3 Apr 2024 15:32:57 +0900 (JST) Date: Wed, 03 Apr 2024 15:32:55 +0900 Message-ID: <87o7arvtuw.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= Cc: Zack Buhman , qemu-devel@nongnu.org, Samuel Tardieu , Aurelien Jarno Subject: Re: [PATCH] sh4: mac.w: memory accesses are 16-bit words In-Reply-To: <16cb6ac0-818b-4393-8b27-20879a150a79@linaro.org> References: <20240402093756.27466-1-zack@buhman.org> <16cb6ac0-818b-4393-8b27-20879a150a79@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Received-SPF: softfail client-ip=153.127.30.23; envelope-from=ysato@users.sourceforge.jp; helo=sakura.ysato.name X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 02 Apr 2024 22:26:25 +0900, Philippe Mathieu-Daud=E9 wrote: >=20 > On 2/4/24 11:37, Zack Buhman wrote: > > Before this change, executing a code sequence such as: > >=20 > > mova tblm,r0 > > mov r0,r1 > > mova tbln,r0 > > clrs > > clrmac > > mac.w @r0+,@r1+ > > mac.w @r0+,@r1+ > >=20 > > .align 4 > > tblm: .word 0x1234 > > .word 0x5678 > > tbln: .word 0x9abc > > .word 0xdefg > >=20 > > Does not result in correct behavior: > >=20 > > Expected behavior: > > first macw : macl =3D 0x1234 * 0x9abc + 0x0 > > mach =3D 0x0 > >=20 > > second macw: macl =3D 0x5678 * 0xdefg + 0xb00a630 > > mach =3D 0x0 > >=20 > > Observed behavior (qemu-sh4eb, prior to this commit): > >=20 > > first macw : macl =3D 0x5678 * 0xdefg + 0x0 > > mach =3D 0x0 > >=20 > > second macw: (unaligned longword memory access, SIGBUS) > >=20 > > Various SH-4 ISA manuals also confirm that `mac.w` is a 16-bit word mem= ory > > access, not a 32-bit longword memory access. > >=20 > > Signed-off-by: Zack Buhman > > --- > > target/sh4/translate.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > >=20 > > diff --git a/target/sh4/translate.c b/target/sh4/translate.c > > index a9b1bc7524..6643c14dde 100644 > > --- a/target/sh4/translate.c > > +++ b/target/sh4/translate.c > > @@ -816,10 +816,10 @@ static void _decode_opc(DisasContext * ctx) > > TCGv arg0, arg1; > > arg0 =3D tcg_temp_new(); > > tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, > > - MO_TESL | MO_ALIGN); > > + MO_TESW | MO_ALIGN); > > arg1 =3D tcg_temp_new(); > > tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, > > - MO_TESL | MO_ALIGN); > > + MO_TESW | MO_ALIGN); >=20 > Apparently invalid since its introduction in commit fdf9b3e831. >=20 > Reviewed-by: Philippe Mathieu-Daud=E9 >=20 > > gen_helper_macw(tcg_env, arg0, arg1); > > tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); > > tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); >=20 SH4 Software manual said. https://www.renesas.com/us/en/document/mas/sh-4-software-manual > This instruction performs signed multiplication of the 16-bit operands > whose addresses are the contents of general registers Rm and Rn, > adds the 32-bit result to the MAC register contents, and stores the > result in the MAC register. Operands Rm and Rn are each incremented > by 2 each time they are read. Reviewed-by: Yoshinori Sato --=20 Yosinori Sato