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Mon, 13 Dec 2021 14:59:12 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0C431AC068; Mon, 13 Dec 2021 14:59:10 +0000 (GMT) Received: from localhost (unknown [9.211.152.7]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Mon, 13 Dec 2021 14:59:09 +0000 (GMT) From: Fabiano Rosas To: =?utf-8?Q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Subject: Re: [PATCH] target/ppc: Fix e6500 boot In-Reply-To: References: <20211213133542.2608540-1-farosas@linux.ibm.com> Date: Mon, 13 Dec 2021 11:59:06 -0300 Message-ID: <87o85kzh39.fsf@linux.ibm.com> Content-Type: text/plain; charset=utf-8 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: b4tUSQbnMJab0PyS80gWtrErpNngMNGE X-Proofpoint-ORIG-GUID: KXNsXwJvoxdgrpaSCKiptWwDZB0vt1Js Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_06,2021-12-13_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=983 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112130093 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, mario@locati.it Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" C=C3=A9dric Le Goater writes: > On 12/13/21 14:35, Fabiano Rosas wrote: >> When Altivec support was added to the e6500 kernel in 2012[1], the >> QEMU code was not changed, so we don't register the VPU/VPUA >> exceptions for the e6500: >>=20 >> qemu: fatal: Raised an exception without defined vector 73 >>=20 >> Note that the error message says 73, instead of 32, which is the IVOR >> for VPU. This is because QEMU knows only knows about the VPU interrupt >> for the 7400s. In theory, we should not be raising _that_ VPU >> interrupt, but instead another one specific for the e6500. >>=20 >> We unfortunately cannot register e6500-specific VPU/VPUA interrupts >> because the SPEU/EFPDI interrupts also use IVOR32/33. These are >> present only in the e500v1/2 versions. From the user manual: >>=20 >> e500v1, e500v2: only SPEU/EFPDI/EFPRI >> e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA >> e6500: only VPU/VPUA >>=20 >> So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code >> to convert the VPU #73 to a #32 when we're in the e6500. Since the >> handling for SPEU and VPU is the same this is the only change that's >> needed. The EFPDI is not implemented and will cause an abort. I don't >> think it worth it changing the error message to take VPUA into >> consideration, so I'm not changing anything there. >>=20 >> This bug was discussed in the thread: >> https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html >>=20 >> 1- https://git.kernel.org/torvalds/c/cd66cc2ee52 >>=20 >> Reported-by: >> Signed-off-by: Fabiano Rosas > > Reviewed-by: C=C3=A9dric Le Goater > > One comment, > >> --- >> target/ppc/cpu_init.c | 6 ++++++ >> target/ppc/excp_helper.c | 12 +++++++++++- >> 2 files changed, 17 insertions(+), 1 deletion(-) >>=20 >> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c >> index 6695985e9b..d8efcb24ed 100644 >> --- a/target/ppc/cpu_init.c >> +++ b/target/ppc/cpu_init.c >> @@ -2273,8 +2273,14 @@ static void init_excp_e200(CPUPPCState *env, targ= et_ulong ivpr_mask) >> env->excp_vectors[POWERPC_EXCP_DTLB] =3D 0x00000000; >> env->excp_vectors[POWERPC_EXCP_ITLB] =3D 0x00000000; >> env->excp_vectors[POWERPC_EXCP_DEBUG] =3D 0x00000000; >> + /* >> + * These two are the same IVOR as POWERPC_EXCP_VPU and >> + * POWERPC_EXCP_VPUA. We deal with that when dispatching at >> + * powerpc_excp(). >> + */ >> env->excp_vectors[POWERPC_EXCP_SPEU] =3D 0x00000000; >> env->excp_vectors[POWERPC_EXCP_EFPDI] =3D 0x00000000; >> + >> env->excp_vectors[POWERPC_EXCP_EFPRI] =3D 0x00000000; >> env->ivor_mask =3D 0x0000FFF7UL; >> env->ivpr_mask =3D ivpr_mask; >> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >> index 17607adbe4..7bb170f440 100644 >> --- a/target/ppc/excp_helper.c >> +++ b/target/ppc/excp_helper.c >> @@ -344,6 +344,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, in= t excp_model, int excp) >> excp =3D POWERPC_EXCP_PROGRAM; >> } >>=20=20=20 >> +#ifdef TARGET_PPC64 >> + /* >> + * SPEU and VPU share the same IVOR but they exist in different >> + * processors. SPEU is e500v1/2 only and VPU is e6500 only. >> + */ >> + if (excp_model =3D=3D POWERPC_EXCP_BOOKE && excp =3D=3D POWERPC_EXC= P_VPU) { >> + excp =3D POWERPC_EXCP_SPEU; >> + } >> +#endif > > I am not in favor of changing powerpc_excp() but I know you have > plans for a major clean up :) Yep, I think is better to fix everything that is broken before the cleanup so we have more code working and being tested before the changes. I would have sent this patch months ago if I knew how to fix it then =3D)