From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AB82C47094 for ; Mon, 7 Jun 2021 10:21:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBCA9610FB for ; Mon, 7 Jun 2021 10:21:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DBCA9610FB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqCOB-00047Q-NY for qemu-devel@archiver.kernel.org; Mon, 07 Jun 2021 06:21:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqCHs-000199-K8 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 06:15:16 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55244) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqCHq-0006rr-Rl for qemu-devel@nongnu.org; Mon, 07 Jun 2021 06:15:16 -0400 Received: by mail-wm1-x32c.google.com with SMTP id o127so9650257wmo.4 for ; Mon, 07 Jun 2021 03:15:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=0tG58hq+kZgcLua2n9MkUg4oj/u62eyv88AkQlbbNfM=; b=ioHfnHMOXSqbGWzqIC/yKaAwq9p0iNi3ap7GXn8XzJp9J7zQozubo5qAEJhIi1h8mD dkoQA/sNRNCVZEtIZliCpjHVrcjwYOtoMkz/2raVlMXWJwrLx6IsZQxjKB6et3TG9MqH h0kFQ8Kke3EDOeArTYynu2Ua2i6gBVE88+hIsUqoO7qdNCTpOnhm5IEAFjK9aqRUz+Wu obS2JOWTySuI37Jcj/TMfvvKyLsfsidSv081zqYGMB6nJS2nSYWVhHWjuC34edcf1De9 Sjkeg68FtCTrz8q7sI/HEP+sZvtkBQ2ts9fdjP5BXEn1oCMTfu7/BN+r5FDvbTRum0ik VT9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=0tG58hq+kZgcLua2n9MkUg4oj/u62eyv88AkQlbbNfM=; b=daRTrEQOFVtzQIWynqOAgz3ZZXAgrYBHjnTior0RGWYl+AUZYYFMY5sspcFjTA7BPo 9wM7flDY7silKtHIv0IjzXNF9gTpNwu7EF0D488OjuBhlGjgERMCUFnBX0ZBUb3N2nvj ihQDc1j/wuHYjm2+8WeYFW1frrLLj06VaOiV8Rq6goz2eWymI6f1JFZdnKAil55nWTom oInK/iFfINU+/M/Ilx7p4uMvefc0zvBnRrSEk41v1lsnEhOQXsfKZQGub5o3KNy4jet0 Y1LBuoLky6o0RRm7flmbsfIE6drLeQe9+nYCO3ITWnxtMhTmCUK55H8pu3TBgbGrvDjW 0Elg== X-Gm-Message-State: AOAM532FkM6PGmxx3RFo6Ydm5+zgz2zdKaSR1DgA+fWurX9FYz3HpodE clRWmTh6pcoc34/eV/6yulTRag== X-Google-Smtp-Source: ABdhPJxs6UQ/5NMokcKRly2f8dYMUl0fUnS0wOUOygAY7SZT29e0kuFomKuSDdDNag0hULmP4RCnGg== X-Received: by 2002:a7b:c761:: with SMTP id x1mr16482896wmk.118.1623060912651; Mon, 07 Jun 2021 03:15:12 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id o11sm394047wmq.1.2021.06.07.03.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 03:15:11 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C8B011FF7E; Mon, 7 Jun 2021 11:15:10 +0100 (BST) References: <65323e52-789c-567a-3446-ccb7709877e2@linaro.org> User-agent: mu4e 1.5.13; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Subject: Re: [RFC] Adding the A64FX's HPC funtions. Date: Mon, 07 Jun 2021 11:14:38 +0100 In-reply-to: Message-ID: <87o8cinfpt.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, Richard Henderson , "qemu-devel@nongnu.org" , "ishii.shuuichir@fujitsu.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Peter Maydell writes: > On Fri, 4 Jun 2021 at 09:29, ishii.shuuichir@fujitsu.com > wrote: >> >> Hi, Richard. >> >> > Well, Peter disagreed with having them enabled by default in -cpu max,= so we >> > might need at least one extra property. I see no reason to have three >> > properties -- one property a64fx-hpc should be sufficient. But we mig= ht not >> > want any command-line properties, see below... >> >> I understood. >> >> > For comparison, in the Arm Cortex-A76 manual, >> > https://developer.arm.com/documentation/100798/0301/ >> > section B2.4 "AArch64 registers by functional group", there is a conci= se >> > listing of all of the system registers and their reset values. >> >> Thank you for the information. >> >> > The most important of these for QEMU to create '-cpu a64fx' are the >> > ID_AA64{ISAR,MMFR,PFR} and MIDR values. These values determine all of >> > the >> > standard architectural features, >> >> The values of ID_AA64{ISAR,MMFR,PFR} and MIDR are not listed in the spec= ifications published at this time. >> Of course, they are listed in the A64FX specification document managed w= ithin Fujitsu, >> but we cannot tell how far these setting values can be disclosed >> without checking with the A64FX specification staff within Fujitsu. > > If somebody has access to A64 hardware they could write a minor kernel > patch to just print the values... We do have access to some a64fx hardware I think... or at least there is some in the lab that tcwg can get access to. > > -- PMM --=20 Alex Benn=C3=A9e