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Thu, 25 Mar 2021 10:19:07 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h12sm1788863wrv.58.2021.03.25.10.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Mar 2021 10:19:06 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6D46E1FF7E; Thu, 25 Mar 2021 17:19:05 +0000 (GMT) References: <20210323041238.133835-1-shashi.mallela@linaro.org> <20210323041238.133835-2-shashi.mallela@linaro.org> User-agent: mu4e 1.5.11; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Shashi Mallela Subject: Re: [PATCH v1 1/8] hw/intc: GICv3 ITS initial framework Date: Thu, 25 Mar 2021 17:18:20 +0000 In-reply-to: <20210323041238.133835-2-shashi.mallela@linaro.org> Message-ID: <87o8f7gnhy.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, leif@nuviainc.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, rad@semihalf.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Shashi Mallela writes: > Added register definitions relevant to ITS,implemented overall > ITS device framework with stubs for ITS control and translater > regions read/write,extended ITS common to handle mmio init between > existing kvm device and newer qemu device. > > Signed-off-by: Shashi Mallela > --- >=20=20 > typedef struct GICv3ITSState GICv3ITSState; > Also could we kernel-doc this function and explain when and why tops would be NULL. > -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops); > +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, > + const MemoryRegionOps *tops); >=20=20 > #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common" > typedef struct GICv3ITSCommonClass GICv3ITSCommonClass; --=20 Alex Benn=C3=A9e