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Tue, 25 Feb 2020 00:12:59 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01P0Cw1q56492404 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 25 Feb 2020 00:12:58 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 430A3C605D; Tue, 25 Feb 2020 00:12:58 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 840E6C6059; Tue, 25 Feb 2020 00:12:57 +0000 (GMT) Received: from localhost (unknown [9.85.139.151]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 25 Feb 2020 00:12:57 +0000 (GMT) From: Fabiano Rosas To: David Gibson , groug@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org Subject: Re: [PATCH v6 05/18] target/ppc: Introduce ppc_hash64_use_vrma() helper In-Reply-To: <20200224233724.46415-6-david@gibson.dropbear.id.au> References: <20200224233724.46415-1-david@gibson.dropbear.id.au> <20200224233724.46415-6-david@gibson.dropbear.id.au> Date: Mon, 24 Feb 2020 21:12:53 -0300 Message-ID: <87o8tn5xtm.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-24_12:2020-02-21, 2020-02-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 spamscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002240181 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , paulus@samba.org, Paolo Bonzini , Igor Mammedov , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" David Gibson writes: > When running guests under a hypervisor, the hypervisor obviously needs to > be protected from guest accesses even if those are in what the guest > considers real mode (translation off). The POWER hardware provides two > ways of doing that: The old way has guest real mode accesses simply offset > and bounds checked into host addresses. It works, but requires that a > significant chunk of the guest's memory - the RMA - be physically > contiguous in the host, which is pretty inconvenient. The new way, known > as VRMA, has guest real mode accesses translated in roughly the normal way > but with some special parameters. > > In POWER7 and POWER8 the LPCR[VPM0] bit selected between the two modes, b= ut > in POWER9 only VRMA mode is supported and LPCR[VPM0] no longer exists. We > handle that difference in behaviour in ppc_hash64_set_isi().. but not in > other places that we blindly check LPCR[VPM0]. > > Correct those instances with a new helper to tell if we should be in VRMA > mode. > > Signed-off-by: David Gibson > Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Fabiano Rosas > --- > target/ppc/mmu-hash64.c | 43 ++++++++++++++++++++--------------------- > 1 file changed, 21 insertions(+), 22 deletions(-) > > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c > index 392f90e0ae..e372c42add 100644 > --- a/target/ppc/mmu-hash64.c > +++ b/target/ppc/mmu-hash64.c > @@ -668,6 +668,21 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU= *cpu, > return 0; > } >=20=20 > +static bool ppc_hash64_use_vrma(CPUPPCState *env) > +{ > + switch (env->mmu_model) { > + case POWERPC_MMU_3_00: > + /* > + * ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR > + * register no longer exist > + */ > + return true; > + > + default: > + return !!(env->spr[SPR_LPCR] & LPCR_VPM0); > + } > +} > + > static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) > { > CPUPPCState *env =3D &POWERPC_CPU(cs)->env; > @@ -676,15 +691,7 @@ static void ppc_hash64_set_isi(CPUState *cs, uint64_= t error_code) > if (msr_ir) { > vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); > } else { > - switch (env->mmu_model) { > - case POWERPC_MMU_3_00: > - /* Field deprecated in ISAv3.00 - interrupts always go to hy= perv */ > - vpm =3D true; > - break; > - default: > - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); > - break; > - } > + vpm =3D ppc_hash64_use_vrma(env); > } > if (vpm && !msr_hv) { > cs->exception_index =3D POWERPC_EXCP_HISI; > @@ -702,15 +709,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, uint64_= t dar, uint64_t dsisr) > if (msr_dr) { > vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); > } else { > - switch (env->mmu_model) { > - case POWERPC_MMU_3_00: > - /* Field deprecated in ISAv3.00 - interrupts always go to hy= perv */ > - vpm =3D true; > - break; > - default: > - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); > - break; > - } > + vpm =3D ppc_hash64_use_vrma(env); > } > if (vpm && !msr_hv) { > cs->exception_index =3D POWERPC_EXCP_HDSI; > @@ -799,7 +798,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, > if (!(eaddr >> 63)) { > raddr |=3D env->spr[SPR_HRMOR]; > } > - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { > + } else if (ppc_hash64_use_vrma(env)) { > /* Emulated VRMA mode */ > slb =3D &env->vrma_slb; > if (!slb->sps) { > @@ -967,7 +966,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu= , target_ulong addr) > } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { > /* In HV mode, add HRMOR if top EA bit is clear */ > return raddr | env->spr[SPR_HRMOR]; > - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { > + } else if (ppc_hash64_use_vrma(env)) { > /* Emulated VRMA mode */ > slb =3D &env->vrma_slb; > if (!slb->sps) { > @@ -1056,8 +1055,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) > slb->sps =3D NULL; >=20=20 > /* Is VRMA enabled ? */ > - lpcr =3D env->spr[SPR_LPCR]; > - if (!(lpcr & LPCR_VPM0)) { > + if (!ppc_hash64_use_vrma(env)) { > return; > } >=20=20 > @@ -1065,6 +1063,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) > * Make one up. Mostly ignore the ESID which will not be needed > * for translation > */ > + lpcr =3D env->spr[SPR_LPCR]; > vsid =3D SLB_VSID_VRMA; > vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; > vsid |=3D (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);