From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59640) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFmji-0005sA-NL for qemu-devel@nongnu.org; Wed, 22 Jun 2016 14:18:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFmje-0006Ok-H8 for qemu-devel@nongnu.org; Wed, 22 Jun 2016 14:18:49 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:35361) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFmje-0006Oe-9k for qemu-devel@nongnu.org; Wed, 22 Jun 2016 14:18:46 -0400 Received: by mail-wm0-x230.google.com with SMTP id v199so97797136wmv.0 for ; Wed, 22 Jun 2016 11:18:46 -0700 (PDT) From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Wed, 22 Jun 2016 19:18:45 +0100 Message-ID: <87oa6tqe7u.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Pranith Kumar , "open list:i386 target" , serge.fdrv@gmail.com Richard Henderson writes: > On 06/22/2016 09:25 AM, Alex Bennée wrote: >> >> Pranith Kumar writes: >> >>> Generate mfence/sfence/lfence instruction on SSE2 enabled >>> processors. For older processors, generate a 'lock orl $0,0(%esp)' >>> instruction which has full ordering semantics. >>> >>> Signed-off-by: Pranith Kumar >>> [rth: Check for sse2, fallback to locked memory op otherwise.] >>> Signed-off-by: Richard Henderson >>> --- >>> tcg/i386/tcg-target.inc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 47 insertions(+) >>> >>> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c >>> index 317484c..0748652 100644 >>> --- a/tcg/i386/tcg-target.inc.c >>> +++ b/tcg/i386/tcg-target.inc.c >>> @@ -121,6 +121,16 @@ static bool have_cmov; >>> # define have_cmov 0 >>> #endif >>> >>> +/* For 32-bit, we are going to attempt to determine at runtime whether >>> + sse2 support is available. */ >>> +#if TCG_TARGET_REG_BITS == 64 || defined(__SSE2__) >> >> Hmm checkpatch.pl warns against including architecture specific defines. >> Is the || leg only going to trigger when building 32 bit x86 with custom >> compiler flags to force SSE2 code? > > Yes, e.g. -march=native. > > I think checkpatch should be ignored in this situation. There's precedent > elsewhere in the tcg backends. And it's definitely architecture specific code. > ;-) Fair enough, I bow to your maintainerly view ;-) -- Alex Bennée