[PATCH] fix: correct typo in ext_zvkb configuration variable Signed-off-by: Kaiyao Duan <inspiremenow@murena.io>

[PATCH] fix: correct typo in ext_zvkb configuration variable Signed-off-by: Kaiyao Duan <inspiremenow@murena.io>

[inspireMeNow]

---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb1a2e7d6d..13cd34adbd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1535,7 +1535,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.0

Re: [PATCH] fix: correct typo in ext_zvkb configuration variable Signed-off-by: Kaiyao Duan <inspiremenow@murena.io>

[Markus Armbruster]

inspireMeNow <inspiremenow@murena.io> writes:

> ---
>  target/riscv/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eb1a2e7d6d..13cd34adbd 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1535,7 +1535,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      /* Vector cryptography extensions */
>      MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
>      MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
> -    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
> +    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
>      MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
>      MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
>      MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),

Commit message should be like

    target/riscv: Correct definition of extension "zvkb"

    Extension "zvkb" accidentally controls "zvkg" instead.  [Brief
    description of the bug's impact]

    Fixes: ea61ef7097d0 (target/riscv: Move vector crypto extensions to riscv_cpu_extensions)
    Signed-off-by: Kaiyao Duan <inspiremenow@murena.io>

Thanks!