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Tue, 17 Jan 2023 18:30:59 +0000 (GMT) References: <20230109014248.2894281-1-richard.henderson@linaro.org> <20230109014248.2894281-18-richard.henderson@linaro.org> User-agent: mu4e 1.9.15; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org Subject: Re: [PATCH v2 17/22] tcg/ppc: Reorg goto_tb implementation Date: Tue, 17 Jan 2023 18:30:13 +0000 In-reply-to: <20230109014248.2894281-18-richard.henderson@linaro.org> Message-ID: <87pmbd109o.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > The old ppc64 implementation replaces 2 or 4 insns, which leaves a race > condition in which a thread could be stopped at a PC in the middle of > the sequence, and when restarted does not see the complete address > computation and branches to nowhere. > > The new implemetation replaces only one insn, swapping between > > b > and > mtctr r31 > > falling through to a general-case indirect branch. > > Signed-off-by: Richard Henderson > --- >=20=20 > static void tcg_out_goto_tb(TCGContext *s, int which) > { > - /* Direct jump. */ > - if (TCG_TARGET_REG_BITS =3D=3D 64) { > - /* Ensure the next insns are 8 or 16-byte aligned. */ > - while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { > - tcg_out32(s, NOP); > - } > + uintptr_t ptr =3D get_jmp_target_addr(s, which); > + > + if (USE_REG_TB) { > + ptrdiff_t offset =3D tcg_tbrel_diff(s, (void *)ptr); > + tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); > +=20=20=20=20 > + /* Direct branch will be patched by tb_target_set_jmp_target. */ > set_jmp_insn_offset(s, which); > - tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); > - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); > tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); > + > + /* When branch is out of range, fall through to indirect. */ > + tcg_out32(s, BCCTR | BO_ALWAYS); > + > + /* For the unlinked case, need to reset TCG_REG_TB. */ > + set_jmp_reset_offset(s, which); > + tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, > + -tcg_current_code_size(s)); > + } else { > + /* Direct branch will be patched by tb_target_set_jmp_target. */ > + set_jmp_insn_offset(s, which); > + tcg_out32(s, NOP); > + > + /* When branch is out of range, fall through to indirect. */ > + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); > + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t= )ptr); > + tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); > tcg_out32(s, BCCTR | BO_ALWAYS); > set_jmp_reset_offset(s, which); > - if (USE_REG_TB) { > - /* For the unlinked case, need to reset TCG_REG_TB. */ > - tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, > - -tcg_current_code_size(s)); > - } > - } else { > - set_jmp_insn_offset(s, which); > - tcg_out32(s, B); > - set_jmp_reset_offset(s, which); > } > } >=20=20 > +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > + uintptr_t jmp_rx, uintptr_t jmp_rw) > +{ > + uintptr_t addr =3D tb->jmp_target_addr[n]; > + intptr_t diff =3D addr - jmp_rx; > + tcg_insn_unit insn; > + > + if (in_range_b(diff)) { > + insn =3D B | (diff & 0x3fffffc); Again deposit would be nice here. > + } else if (USE_REG_TB) { > + insn =3D MTSPR | RS(TCG_REG_TB) | CTR; > + } else { > + insn =3D NOP; > + } > + > + qatomic_set((uint32_t *)jmp_rw, insn); > + flush_idcache_range(jmp_rx, jmp_rw, 4); > +} > + > static void tcg_out_op(TCGContext *s, TCGOpcode opc, > const TCGArg args[TCG_MAX_OP_ARGS], > const int const_args[TCG_MAX_OP_ARGS]) Otherwise: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro