From: Fabiano Rosas <farosas@linux.ibm.com>
To: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>,
qemu-devel@nongnu.org
Cc: lucas.araujo@eldorado.org.br, luis.pires@eldorado.org.br,
fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org,
"Bruno Larsen \(billionai\)" <bruno.larsen@eldorado.org.br>,
matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: Re: [RFC PATCH 1/4] target/ppc: move opcode table logic to translate.c
Date: Mon, 26 Apr 2021 16:15:23 -0300 [thread overview]
Message-ID: <87pmyg3lis.fsf@linux.ibm.com> (raw)
In-Reply-To: <20210423191807.77963-2-bruno.larsen@eldorado.org.br>
"Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br> writes:
> code motion to remove opcode callback table from
> translate_init.c.inc to translate.c in preparation
> to remove #include <translate_init.c.inc> from
> translate.c
I'd mention the creation of destroy_ppc_opcodes since this patch is not
strictly just moving code.
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> ---
> target/ppc/internal.h | 6 +
> target/ppc/translate.c | 394 ++++++++++++++++++++++++++++++++
> target/ppc/translate_init.c.inc | 390 +------------------------------
> 3 files changed, 401 insertions(+), 389 deletions(-)
<snip>
> +void destroy_ppc_opcodes(PowerPCCPU *cpu)
> +{
> + opc_handler_t **table, **table_2;
> + int i, j, k;
> +
> + for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
> + if (cpu->opcodes[i] == &invalid_handler) {
> + continue;
> + }
> + if (is_indirect_opcode(cpu->opcodes[i])) {
> + table = ind_table(cpu->opcodes[i]);
> + for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
> + if (table[j] == &invalid_handler) {
> + continue;
> + }
> + if (is_indirect_opcode(table[j])) {
> + table_2 = ind_table(table[j]);
> + for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
> + if (table_2[k] != &invalid_handler &&
> + is_indirect_opcode(table_2[k])) {
> + g_free((opc_handler_t *)((uintptr_t)table_2[k] &
> + ~PPC_INDIRECT));
> + }
> + }
> + g_free((opc_handler_t *)((uintptr_t)table[j] &
> + ~PPC_INDIRECT));
> + }
> + }
> + g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
> + ~PPC_INDIRECT));
> + }
> + }
> +}
> +
> +#if defined(PPC_DUMP_CPU)
The commented out define for this was left behind.
> +static void dump_ppc_insns(CPUPPCState *env)
> +{
> + opc_handler_t **table, *handler;
> + const char *p, *q;
> + uint8_t opc1, opc2, opc3, opc4;
> +
> + printf("Instructions set:\n");
> + /* opc1 is 6 bits long */
> + for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
> + table = env->opcodes;
> + handler = table[opc1];
> + if (is_indirect_opcode(handler)) {
> + /* opc2 is 5 bits long */
> + for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
> + table = env->opcodes;
> + handler = env->opcodes[opc1];
> + table = ind_table(handler);
> + handler = table[opc2];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + /* opc3 is 5 bits long */
> + for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
> + opc3++) {
> + handler = table[opc3];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + /* opc4 is 5 bits long */
> + for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
> + opc4++) {
> + handler = table[opc4];
> + if (handler->handler != &gen_invalid) {
> + printf("INSN: %02x %02x %02x %02x -- "
> + "(%02d %04d %02d) : %s\n",
> + opc1, opc2, opc3, opc4,
> + opc1, (opc3 << 5) | opc2, opc4,
> + handler->oname);
> + }
> + }
> + } else {
> + if (handler->handler != &gen_invalid) {
> + /* Special hack to properly dump SPE insns */
> + p = strchr(handler->oname, '_');
> + if (p == NULL) {
> + printf("INSN: %02x %02x %02x (%02d %04d) : "
> + "%s\n",
> + opc1, opc2, opc3, opc1,
> + (opc3 << 5) | opc2,
> + handler->oname);
> + } else {
> + q = "speundef";
> + if ((p - handler->oname) != strlen(q)
> + || (memcmp(handler->oname, q, strlen(q))
> + != 0)) {
> + /* First instruction */
> + printf("INSN: %02x %02x %02x"
> + "(%02d %04d) : %.*s\n",
> + opc1, opc2 << 1, opc3, opc1,
> + (opc3 << 6) | (opc2 << 1),
> + (int)(p - handler->oname),
> + handler->oname);
> + }
> + if (strcmp(p + 1, q) != 0) {
> + /* Second instruction */
> + printf("INSN: %02x %02x %02x "
> + "(%02d %04d) : %s\n", opc1,
> + (opc2 << 1) | 1, opc3, opc1,
> + (opc3 << 6) | (opc2 << 1) | 1,
> + p + 1);
> + }
> + }
> + }
> + }
> + }
> + } else {
> + if (handler->handler != &gen_invalid) {
> + printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
> + opc1, opc2, opc1, opc2, handler->oname);
> + }
> + }
> + }
> + } else {
> + if (handler->handler != &gen_invalid) {
> + printf("INSN: %02x -- -- (%02d ----) : %s\n",
> + opc1, opc1, handler->oname);
> + }
> + }
> + }
> +}
> +#endif
next prev parent reply other threads:[~2021-04-26 19:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-23 19:18 [RFC PATCH 0/4] target/ppc: code motion to compile translate_init Bruno Larsen (billionai)
2021-04-23 19:18 ` [RFC PATCH 1/4] target/ppc: move opcode table logic to translate.c Bruno Larsen (billionai)
2021-04-26 19:15 ` Fabiano Rosas [this message]
2021-04-26 19:29 ` Bruno Piazera Larsen
2021-04-27 3:16 ` david
2021-04-23 19:18 ` [RFC PATCH 2/4] target/ppc: isolated SPR read/write callbacks Bruno Larsen (billionai)
2021-04-26 20:06 ` Fabiano Rosas
2021-04-26 20:38 ` Bruno Piazera Larsen
2021-04-27 3:28 ` David Gibson
2021-04-23 19:18 ` [RFC PATCH 3/4] target/ppc: Move SPR generation to separate file Bruno Larsen (billionai)
2021-04-26 21:08 ` Fabiano Rosas
2021-04-27 3:35 ` David Gibson
2021-04-23 19:18 ` [RFC PATCH 4/4] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
2021-04-27 3:38 ` David Gibson
2021-04-23 23:43 ` [RFC PATCH 0/4] target/ppc: code motion to compile translate_init Richard Henderson
2021-04-26 11:51 ` Bruno Piazera Larsen
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