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X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Include definitions for all of the bits in ID_MMFR3. > We already have a definition for ID_AA64MMFR1.PAN. > > Reviewed-by: Peter Maydell > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/cpu.h | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index c63bceaaa5..08b2f5d73e 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1727,6 +1727,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) > FIELD(ID_ISAR6, SB, 12, 4) > FIELD(ID_ISAR6, SPECRES, 16, 4) >=20=20 > +FIELD(ID_MMFR3, CMAINTVA, 0, 4) > +FIELD(ID_MMFR3, CMAINTSW, 4, 4) > +FIELD(ID_MMFR3, BPMAINT, 8, 4) > +FIELD(ID_MMFR3, MAINTBCST, 12, 4) > +FIELD(ID_MMFR3, PAN, 16, 4) > +FIELD(ID_MMFR3, COHWALK, 20, 4) > +FIELD(ID_MMFR3, CMEMSZ, 24, 4) > +FIELD(ID_MMFR3, SUPERSEC, 28, 4) > + > FIELD(ID_MMFR4, SPECSEI, 0, 4) > FIELD(ID_MMFR4, AC2, 4, 4) > FIELD(ID_MMFR4, XNX, 8, 4) > @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(con= st ARMISARegisters *id) > return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; > } >=20=20 > +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) !=3D 0; > +} > + > +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; > +} > + > /* > * 64-bit feature tests via id registers. > */ > @@ -3602,6 +3621,16 @@ static inline bool isar_feature_aa64_lor(const ARM= ISARegisters *id) > return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; > } >=20=20 > +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; > +} > + > +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; > +} > + > static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) > { > return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; --=20 Alex Benn=C3=A9e