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From: Anthony Liguori <anthony@codemonkey.ws>
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References: <cover.1371881222.git.jan.kiszka@web.de>
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	<51C75FA6.6080903@reactos.org> <51C7E21A.9090005@web.de>
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Date: Fri, 12 Jul 2013 07:56:42 -0500
Message-ID: <87ppuoc4xh.fsf@codemonkey.ws>
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Subject: Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to
	memory core layer
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To: Alexander Graf <agraf@suse.de>, Jan Kiszka <jan.kiszka@web.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Liu Ping Fan <pingfank@linux.vnet.ibm.com>, =?utf-8?Q?Herv=C3=A9?= Poussineau <hpoussin@reactos.org>, qemu-devel <qemu-devel@nongnu.org>, Andreas =?utf-8?Q?F=C3=A4rber?= <afaerber@suse.de>

Alexander Graf <agraf@suse.de> writes:

> On 11.07.2013, at 14:29, Alexander Graf wrote:
>
>> This patch breaks VGA on PPC as it is in master today.
>
> If I don't mark portio as little endian it works as expected. There's
> probably someone swapping things twice.

This is the correct fix.  Can you please send a patch?

I/O dispatch functions take a native endian argument and when
cpu_{in,out][bwl] is called it's passed a native endian argument.  There
is no need to ever byte swap.

The ISA bus is going to have data pins numbered D0..D15.  There is no
concept of endianness.  D0 is the LSB.  How the CPU stores bytes in
memory is orthogonal to what is happening on the bus.

Regards,

Anthony Liguori

>
>
> Alex