[Qemu-devel] [PATCH] fix configure for mips o32

[Qemu-devel] [PATCH] fix configure for mips o32

[Arnaud Patard]

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The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
target_phys_bits and set it to 64 for all mips machines including mipsel
machines which are 32 bit. This patch set it to 32.

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
---

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Index: qemu/configure
===================================================================
--- qemu.orig/configure
+++ qemu/configure
@@ -1970,7 +1970,7 @@ case "$target_cpu" in
     echo "#define TARGET_ARCH \"mips\"" >> $config_h
     echo "#define TARGET_MIPS 1" >> $config_h
     echo "#define TARGET_ABI_MIPSO32 1" >> $config_h
-    target_phys_bits=64
+    target_phys_bits=32
   ;;
   mipsn32|mipsn32el)
     echo "TARGET_ARCH=mipsn32" >> $config_mak

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[M. Warner Losh]

In message: <87prdlv6wf.fsf@lechat.rtp-net.org>
            Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> writes:
: The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
: target_phys_bits and set it to 64 for all mips machines including mipsel
: machines which are 32 bit. This patch set it to 32.

But R4000PC and R4400PC machines ran in Little Endian mode and had
64-bit registers.

It is only the recent mips32 and mips32r2 machines that have 32-bit
registers...

Warner

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[Arnaud Patard]

"M. Warner Losh" <imp@bsdimp.com> writes:

> In message: <87prdlv6wf.fsf@lechat.rtp-net.org>
>             Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> writes:
> : The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
> : target_phys_bits and set it to 64 for all mips machines including mipsel
> : machines which are 32 bit. This patch set it to 32.
>
> But R4000PC and R4400PC machines ran in Little Endian mode and had
> 64-bit registers.
>
> It is only the recent mips32 and mips32r2 machines that have 32-bit
> registers...

I'm sorry but I don't get your point. Qemu should work on all cpu. 4Kc &
friends are currently supports (according to the -M switch) and iirc
theses beasts have 32bit address path not 64. I really fear that setting
64 will break them. That's why I've sent this patch. If keeping 64bit
breaks 4Kc and if switching to 32 break r4k, an other solution will have
to be found imho


Arnaud

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[Paul Brook]

On Wednesday 03 June 2009, Arnaud Patard wrote:
> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
> target_phys_bits and set it to 64 for all mips machines including mipsel
> machines which are 32 bit. This patch set it to 32.

MIPS32 CPUs have a 36-bit physical address space. That's what the old code 
said anyway.

Paul

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[Arnaud Patard]

Paul Brook <paul@codesourcery.com> writes:

> On Wednesday 03 June 2009, Arnaud Patard wrote:
>> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
>> target_phys_bits and set it to 64 for all mips machines including mipsel
>> machines which are 32 bit. This patch set it to 32.
>
> MIPS32 CPUs have a 36-bit physical address space. That's what the old code 
> said anyway.

Is there more information than that in the old code ? I really thought
mips32 4Kc have 32-bit address paths not 36.

Arnaud

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[Paul Brook]

On Wednesday 03 June 2009, Arnaud Patard wrote:
> Paul Brook <paul@codesourcery.com> writes:
> > On Wednesday 03 June 2009, Arnaud Patard wrote:
> >> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
> >> target_phys_bits and set it to 64 for all mips machines including mipsel
> >> machines which are 32 bit. This patch set it to 32.
> >
> > MIPS32 CPUs have a 36-bit physical address space. That's what the old
> > code said anyway.
>
> Is there more information than that in the old code ? I really thought
> mips32 4Kc have 32-bit address paths not 36.

I suspect you're confusing physical and virtual addresses.

> I really fear that setting 64 will break them.

If this were true they'd already be broken on 64-bit hosts.

Paul

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[Arnaud Patard]

Paul Brook <paul@codesourcery.com> writes:

Hi,

> On Wednesday 03 June 2009, Arnaud Patard wrote:
>> Paul Brook <paul@codesourcery.com> writes:
>> > On Wednesday 03 June 2009, Arnaud Patard wrote:
>> >> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
>> >> target_phys_bits and set it to 64 for all mips machines including mipsel
>> >> machines which are 32 bit. This patch set it to 32.
>> >
>> > MIPS32 CPUs have a 36-bit physical address space. That's what the old
>> > code said anyway.
>>
>> Is there more information than that in the old code ? I really thought
>> mips32 4Kc have 32-bit address paths not 36.
>
> I suspect you're confusing physical and virtual addresses.
>

fwiw, found out where I read that. At
http://www.mips.com/products/processors/hard-ip-cores/4kc-hard-ip-core/.


Arnaud

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[M. Warner Losh]

In message: <87r5y0tkzg.fsf@lechat.rtp-net.org>
            Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> writes:
: Paul Brook <paul@codesourcery.com> writes:
: 
: Hi,
: 
: > On Wednesday 03 June 2009, Arnaud Patard wrote:
: >> Paul Brook <paul@codesourcery.com> writes:
: >> > On Wednesday 03 June 2009, Arnaud Patard wrote:
: >> >> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
: >> >> target_phys_bits and set it to 64 for all mips machines including mipsel
: >> >> machines which are 32 bit. This patch set it to 32.
: >> >
: >> > MIPS32 CPUs have a 36-bit physical address space. That's what the old
: >> > code said anyway.
: >>
: >> Is there more information than that in the old code ? I really thought
: >> mips32 4Kc have 32-bit address paths not 36.
: >
: > I suspect you're confusing physical and virtual addresses.
: >
: 
: fwiw, found out where I read that. At
: http://www.mips.com/products/processors/hard-ip-cores/4kc-hard-ip-core/.

None-the-less, mipsel for arc has 36-bit addresses.  The patch is bad.

Warner

Re: [Qemu-devel] [PATCH] fix configure for mips o32

[M. Warner Losh]

In message: <87ws7ttkch.fsf@lechat.rtp-net.org>
            Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> writes:
: Paul Brook <paul@codesourcery.com> writes:
: 
: > On Wednesday 03 June 2009, Arnaud Patard wrote:
: >> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
: >> target_phys_bits and set it to 64 for all mips machines including mipsel
: >> machines which are 32 bit. This patch set it to 32.
: >
: > MIPS32 CPUs have a 36-bit physical address space. That's what the old code 
: > said anyway.
: 
: Is there more information than that in the old code ? I really thought
: mips32 4Kc have 32-bit address paths not 36.

Are you talking virtual addresses or physical addresses?  arc machines
are little endian and have 36-bit physical addresses because they are
based on the r4400 processors.  And much of the hardware is located
above 4GB, so needs to be accessed through special TLB entries.

Of course, this is orthogonal to my original point: mipsel and mips
specify the endian of the machines, not the underlying size.

Warner