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X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Christophe Lyon , richard.henderson@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Christophe Lyon writes: > This is derived from cortex-m4 description, adding DP support and FPv5 > instructions with the corresponding flags in isar and mvfr2. > > Checked that it could successfully execute > vrinta.f32 s15, s15 > while cortex-m4 emulation rejects it with "illegal instruction". I couldn't verify the cpu->midr values as most of the sections seem to be IMPDEF but the rest of the feature bits look OK to me: Reviewed-by: Alex Benn=C3=A9e > > Signed-off-by: Christophe Lyon > --- > target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 13813fb..ccae849 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1954,6 +1954,37 @@ static void cortex_m4_initfn(Object *obj) > cpu->isar.id_isar6 =3D 0x00000000; > } > > +static void cortex_m7_initfn(Object *obj) > +{ > + ARMCPU *cpu =3D ARM_CPU(obj); > + > + set_feature(&cpu->env, ARM_FEATURE_V7); > + set_feature(&cpu->env, ARM_FEATURE_M); > + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); > + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); > + set_feature(&cpu->env, ARM_FEATURE_VFP4); > + cpu->midr =3D 0x411fc272; /* r1p2 */ > + cpu->pmsav7_dregion =3D 8; > + cpu->isar.mvfr0 =3D 0x10110221; > + cpu->isar.mvfr1 =3D 0x12000011; > + cpu->isar.mvfr2 =3D 0x00000040; > + cpu->id_pfr0 =3D 0x00000030; > + cpu->id_pfr1 =3D 0x00000200; > + cpu->id_dfr0 =3D 0x00100000; > + cpu->id_afr0 =3D 0x00000000; > + cpu->id_mmfr0 =3D 0x00100030; > + cpu->id_mmfr1 =3D 0x00000000; > + cpu->id_mmfr2 =3D 0x01000000; > + cpu->id_mmfr3 =3D 0x00000000; > + cpu->isar.id_isar0 =3D 0x01101110; > + cpu->isar.id_isar1 =3D 0x02112000; > + cpu->isar.id_isar2 =3D 0x20232231; > + cpu->isar.id_isar3 =3D 0x01111131; > + cpu->isar.id_isar4 =3D 0x01310132; > + cpu->isar.id_isar5 =3D 0x00000000; > + cpu->isar.id_isar6 =3D 0x00000000; > +} > + > static void cortex_m33_initfn(Object *obj) > { > ARMCPU *cpu =3D ARM_CPU(obj); > @@ -2538,6 +2569,8 @@ static const ARMCPUInfo arm_cpus[] =3D { > .class_init =3D arm_v7m_class_init }, > { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, > .class_init =3D arm_v7m_class_init }, > + { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, > + .class_init =3D arm_v7m_class_init }, > { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, > .class_init =3D arm_v7m_class_init }, > { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, -- Alex Benn=C3=A9e