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X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, stefanha@redhat.com, david@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > There is only one caller, tlb_set_page_with_attrs. We cannot > inline the entire function because the AddressSpaceDispatch > structure is private to exec.c, and cannot easily be moved to > include/exec/memory-internal.h. > > Compute is_ram and is_romd once within tlb_set_page_with_attrs. > Fold the number of tests against these predicates. Compute > cpu_physical_memory_is_clean outside of the tlb lock region. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > include/exec/exec-all.h | 6 +--- > accel/tcg/cputlb.c | 68 ++++++++++++++++++++++++++--------------- > exec.c | 22 ++----------- > 3 files changed, 47 insertions(+), 49 deletions(-) > > diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h > index 81b02eb2fe..49db07ba0b 100644 > --- a/include/exec/exec-all.h > +++ b/include/exec/exec-all.h > @@ -509,11 +509,7 @@ address_space_translate_for_iotlb(CPUState *cpu, int= asidx, hwaddr addr, > hwaddr *xlat, hwaddr *plen, > MemTxAttrs attrs, int *prot); > hwaddr memory_region_section_get_iotlb(CPUState *cpu, > - MemoryRegionSection *section, > - target_ulong vaddr, > - hwaddr paddr, hwaddr xlat, > - int prot, > - target_ulong *address); > + MemoryRegionSection *section); > #endif > > /* vl.c */ > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 05212ff244..05530a8b0c 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -704,13 +704,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, > MemoryRegionSection *section; > unsigned int index; > target_ulong address; > - target_ulong code_address; > + target_ulong write_address; > uintptr_t addend; > CPUTLBEntry *te, tn; > hwaddr iotlb, xlat, sz, paddr_page; > target_ulong vaddr_page; > int asidx =3D cpu_asidx_from_attrs(cpu, attrs); > int wp_flags; > + bool is_ram, is_romd; > > assert_cpu_is_self(cpu); > > @@ -739,18 +740,46 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, > if (attrs.byte_swap) { > address |=3D TLB_BSWAP; > } > - if (!memory_region_is_ram(section->mr) && > - !memory_region_is_romd(section->mr)) { > - /* IO memory case */ > - address |=3D TLB_MMIO; > - addend =3D 0; > - } else { > + > + is_ram =3D memory_region_is_ram(section->mr); > + is_romd =3D memory_region_is_romd(section->mr); > + > + if (is_ram || is_romd) { > + /* RAM and ROMD both have associated host memory. */ > addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + x= lat; > + } else { > + /* I/O does not; force the host address to NULL. */ > + addend =3D 0; > + } > + > + write_address =3D address; > + if (is_ram) { > + iotlb =3D memory_region_get_ram_addr(section->mr) + xlat; > + /* > + * Computing is_clean is expensive; avoid all that unless > + * the page is actually writable. > + */ > + if (prot & PAGE_WRITE) { > + if (section->readonly) { > + write_address |=3D TLB_ROM; > + } else if (cpu_physical_memory_is_clean(iotlb)) { > + write_address |=3D TLB_NOTDIRTY; > + } > + } > + } else { > + /* I/O or ROMD */ > + iotlb =3D memory_region_section_get_iotlb(cpu, section) + xlat; > + /* > + * Writes to romd devices must go through MMIO to enable write. > + * Reads to romd devices go through the ram_ptr found above, > + * but of course reads to I/O must go through MMIO. > + */ > + write_address |=3D TLB_MMIO; > + if (!is_romd) { > + address =3D write_address; > + } > } > > - code_address =3D address; > - iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, > - paddr_page, xlat, prot, &add= ress); > wp_flags =3D cpu_watchpoint_address_matches(cpu, vaddr_page, > TARGET_PAGE_SIZE); > > @@ -790,8 +819,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, > /* > * At this point iotlb contains a physical section number in the low= er > * TARGET_PAGE_BITS, and either > - * + the ram_addr_t of the page base of the target RAM (if NOTDIRTY= or ROM) > - * + the offset within section->mr of the page base (otherwise) > + * + the ram_addr_t of the page base of the target RAM (RAM) > + * + the offset within section->mr of the page base (I/O, ROMD) > * We subtract the vaddr_page (which is page aligned and thus won't > * disturb the low bits) to give an offset which can be added to the > * (non-page-aligned) vaddr of the eventual memory access to get > @@ -814,25 +843,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, > } > > if (prot & PAGE_EXEC) { > - tn.addr_code =3D code_address; > + tn.addr_code =3D address; > } else { > tn.addr_code =3D -1; > } > > tn.addr_write =3D -1; > if (prot & PAGE_WRITE) { > - tn.addr_write =3D address; > - if (memory_region_is_romd(section->mr)) { > - /* Use the MMIO path so that the device can switch states. */ > - tn.addr_write |=3D TLB_MMIO; > - } else if (memory_region_is_ram(section->mr)) { > - if (section->readonly) { > - tn.addr_write |=3D TLB_ROM; > - } else if (cpu_physical_memory_is_clean( > - memory_region_get_ram_addr(section->mr) + xlat))= { > - tn.addr_write |=3D TLB_NOTDIRTY; > - } > - } > + tn.addr_write =3D write_address; > if (prot & PAGE_WRITE_INV) { > tn.addr_write |=3D TLB_INVALID_MASK; > } > diff --git a/exec.c b/exec.c > index dc7001f115..961d7d6497 100644 > --- a/exec.c > +++ b/exec.c > @@ -1459,26 +1459,10 @@ bool cpu_physical_memory_snapshot_get_dirty(Dirty= BitmapSnapshot *snap, > > /* Called from RCU critical section */ > hwaddr memory_region_section_get_iotlb(CPUState *cpu, > - MemoryRegionSection *section, > - target_ulong vaddr, > - hwaddr paddr, hwaddr xlat, > - int prot, > - target_ulong *address) > + MemoryRegionSection *section) > { > - hwaddr iotlb; > - > - if (memory_region_is_ram(section->mr)) { > - /* Normal RAM. */ > - iotlb =3D memory_region_get_ram_addr(section->mr) + xlat; > - } else { > - AddressSpaceDispatch *d; > - > - d =3D flatview_to_dispatch(section->fv); > - iotlb =3D section - d->map.sections; > - iotlb +=3D xlat; > - } > - > - return iotlb; > + AddressSpaceDispatch *d =3D flatview_to_dispatch(section->fv); > + return section - d->map.sections; > } > #endif /* defined(CONFIG_USER_ONLY) */ -- Alex Benn=C3=A9e