From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46427) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3fbZ-00027t-3T for qemu-devel@nongnu.org; Wed, 04 Apr 2018 06:25:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3fbU-0001Ti-ME for qemu-devel@nongnu.org; Wed, 04 Apr 2018 06:25:25 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:36612) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f3fbU-0001T9-2N for qemu-devel@nongnu.org; Wed, 04 Apr 2018 06:25:20 -0400 Received: by mail-wm0-x244.google.com with SMTP id x82so41010860wmg.1 for ; Wed, 04 Apr 2018 03:25:19 -0700 (PDT) References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> <1519324303-5674-6-git-send-email-aleksandar.markovic@rt-rk.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1519324303-5674-6-git-send-email-aleksandar.markovic@rt-rk.com> Date: Wed, 04 Apr 2018 11:25:17 +0100 Message-ID: <87r2nvclpu.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 5/6] hw/mips_cpc: kick a VP when putting it into Run state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aleksandar Markovic Cc: qemu-devel@nongnu.org, Aurelien Jarno , Fam Zheng , Gerd Hoffmann , Laurent Vivier , Paolo Bonzini , Peter Maydell , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson , Riku Voipio , Yongbok Kim , Aleksandar Markovic , Goran Ferenc , Miodrag Dinic , Petar Jovanovic , Raghu Gandham Aleksandar Markovic writes: > From: Miodrag Dinic > > While testing mttcg VP0 could get stuck in a loop waiting for other > VPs to come up (which never actually happens). To fix this, kick VPs > while they are being powered up by Cluster Power Controller in an > async task which is triggered once the host thread is being spawned. > > Signed-off-by: Miodrag Dinic > Signed-off-by: Leon Alrae > Signed-off-by: Aleksandar Markovic Reviewed-by: Alex Benn=C3=A9e > --- > hw/misc/mips_cpc.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c > index 6d34574..712d842 100644 > --- a/hw/misc/mips_cpc.c > +++ b/hw/misc/mips_cpc.c > @@ -30,6 +30,14 @@ static inline uint64_t cpc_vp_run_mask(MIPSCPCState *c= pc) > return (1ULL << cpc->num_vp) - 1; > } > > +static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) > +{ > + MIPSCPCState *cpc =3D (MIPSCPCState *) data.host_ptr; > + > + cpu_reset(cs); > + cpc->vp_running |=3D 1ULL << cs->cpu_index; > +} > + > static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) > { > CPUState *cs =3D first_cpu; > @@ -37,8 +45,13 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_= run) > CPU_FOREACH(cs) { > uint64_t i =3D 1ULL << cs->cpu_index; > if (i & vp_run & ~cpc->vp_running) { > - cpu_reset(cs); > - cpc->vp_running |=3D i; > + /* > + * To avoid racing with a CPU we are just kicking off. > + * We do the final bit of preparation for the work in > + * the target CPUs context. > + */ > + async_safe_run_on_cpu(cs, mips_cpu_reset_async_work, > + RUN_ON_CPU_HOST_PTR(cpc)); > } > } > } -- Alex Benn=C3=A9e