From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v11 08/20] tcg: Add generic helpers for saturating arithmetic
Date: Tue, 06 Feb 2018 11:03:15 +0000 [thread overview]
Message-ID: <87r2pywfbg.fsf@linaro.org> (raw)
In-Reply-To: <20180126045742.5487-9-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> No vector ops as yet. SSE only has direct support for 8- and 16-bit
> saturation; handling 32- and 64-bit saturation is much more expensive.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> accel/tcg/tcg-runtime.h | 20 ++++
> tcg/tcg-op-gvec.h | 10 ++
> accel/tcg/tcg-runtime-gvec.c | 268 +++++++++++++++++++++++++++++++++++++++++++
> tcg/tcg-op-gvec.c | 92 +++++++++++++++
> 4 files changed, 390 insertions(+)
>
> diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
> index 54f7e78b09..f224a975e8 100644
> --- a/accel/tcg/tcg-runtime.h
> +++ b/accel/tcg/tcg-runtime.h
> @@ -157,6 +157,26 @@ DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
>
> +DEF_HELPER_FLAGS_4(gvec_ssadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_ssadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_ssadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_ssadd64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> +DEF_HELPER_FLAGS_4(gvec_sssub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_sssub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_sssub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_sssub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> +DEF_HELPER_FLAGS_4(gvec_usadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_usadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_usadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_usadd64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> +DEF_HELPER_FLAGS_4(gvec_ussub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_ussub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_ussub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_4(gvec_ussub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
> +
> DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
> DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
> DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
> diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
> index abe909df39..03ced440c2 100644
> --- a/tcg/tcg-op-gvec.h
> +++ b/tcg/tcg-op-gvec.h
> @@ -179,6 +179,16 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
> void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
>
> +/* Saturated arithmetic. */
> +void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
> +void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
> +void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
> +void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
> +
> void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
> void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
> diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
> index 59d7a0a2fe..e6f99babcd 100644
> --- a/accel/tcg/tcg-runtime-gvec.c
> +++ b/accel/tcg/tcg-runtime-gvec.c
> @@ -547,3 +547,271 @@ DO_CMP2(64)
> #undef DO_CMP0
> #undef DO_CMP1
> #undef DO_CMP2
> +
> +void HELPER(gvec_ssadd8)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int8_t)) {
> + int r = *(int8_t *)(a + i) + *(int8_t *)(b + i);
> + if (r > INT8_MAX) {
> + r = INT8_MAX;
> + } else if (r < INT8_MIN) {
> + r = INT8_MIN;
> + }
> + *(int8_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ssadd16)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int16_t)) {
> + int r = *(int16_t *)(a + i) + *(int16_t *)(b + i);
> + if (r > INT16_MAX) {
> + r = INT16_MAX;
> + } else if (r < INT16_MIN) {
> + r = INT16_MIN;
> + }
> + *(int16_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ssadd32)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int32_t)) {
> + int32_t ai = *(int32_t *)(a + i);
> + int32_t bi = *(int32_t *)(b + i);
> + int32_t di = ai + bi;
> + if (((di ^ ai) &~ (ai ^ bi)) < 0) {
> + /* Signed overflow. */
> + di = (di < 0 ? INT32_MAX : INT32_MIN);
> + }
> + *(int32_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ssadd64)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int64_t)) {
> + int64_t ai = *(int64_t *)(a + i);
> + int64_t bi = *(int64_t *)(b + i);
> + int64_t di = ai + bi;
> + if (((di ^ ai) &~ (ai ^ bi)) < 0) {
> + /* Signed overflow. */
> + di = (di < 0 ? INT64_MAX : INT64_MIN);
> + }
> + *(int64_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_sssub8)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
> + int r = *(int8_t *)(a + i) - *(int8_t *)(b + i);
> + if (r > INT8_MAX) {
> + r = INT8_MAX;
> + } else if (r < INT8_MIN) {
> + r = INT8_MIN;
> + }
> + *(uint8_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_sssub16)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int16_t)) {
> + int r = *(int16_t *)(a + i) - *(int16_t *)(b + i);
> + if (r > INT16_MAX) {
> + r = INT16_MAX;
> + } else if (r < INT16_MIN) {
> + r = INT16_MIN;
> + }
> + *(int16_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_sssub32)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int32_t)) {
> + int32_t ai = *(int32_t *)(a + i);
> + int32_t bi = *(int32_t *)(b + i);
> + int32_t di = ai - bi;
> + if (((di ^ ai) & (ai ^ bi)) < 0) {
> + /* Signed overflow. */
> + di = (di < 0 ? INT32_MAX : INT32_MIN);
> + }
> + *(int32_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_sssub64)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(int64_t)) {
> + int64_t ai = *(int64_t *)(a + i);
> + int64_t bi = *(int64_t *)(b + i);
> + int64_t di = ai - bi;
> + if (((di ^ ai) & (ai ^ bi)) < 0) {
> + /* Signed overflow. */
> + di = (di < 0 ? INT64_MAX : INT64_MIN);
> + }
> + *(int64_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_usadd8)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
> + unsigned r = *(uint8_t *)(a + i) + *(uint8_t *)(b + i);
> + if (r > UINT8_MAX) {
> + r = UINT8_MAX;
> + }
> + *(uint8_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_usadd16)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
> + unsigned r = *(uint16_t *)(a + i) + *(uint16_t *)(b + i);
> + if (r > UINT16_MAX) {
> + r = UINT16_MAX;
> + }
> + *(uint16_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_usadd32)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
> + uint32_t ai = *(uint32_t *)(a + i);
> + uint32_t bi = *(uint32_t *)(b + i);
> + uint32_t di = ai + bi;
> + if (di < ai) {
> + di = UINT32_MAX;
> + }
> + *(uint32_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_usadd64)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
> + uint64_t ai = *(uint64_t *)(a + i);
> + uint64_t bi = *(uint64_t *)(b + i);
> + uint64_t di = ai + bi;
> + if (di < ai) {
> + di = UINT64_MAX;
> + }
> + *(uint64_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ussub8)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
> + int r = *(uint8_t *)(a + i) - *(uint8_t *)(b + i);
> + if (r < 0) {
> + r = 0;
> + }
> + *(uint8_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ussub16)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
> + int r = *(uint16_t *)(a + i) - *(uint16_t *)(b + i);
> + if (r < 0) {
> + r = 0;
> + }
> + *(uint16_t *)(d + i) = r;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ussub32)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
> + uint32_t ai = *(uint32_t *)(a + i);
> + uint32_t bi = *(uint32_t *)(b + i);
> + uint32_t di = ai - bi;
> + if (ai < bi) {
> + di = 0;
> + }
> + *(uint32_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> +
> +void HELPER(gvec_ussub64)(void *d, void *a, void *b, uint32_t desc)
> +{
> + intptr_t oprsz = simd_oprsz(desc);
> + intptr_t i;
> +
> + for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
> + uint64_t ai = *(uint64_t *)(a + i);
> + uint64_t bi = *(uint64_t *)(b + i);
> + uint64_t di = ai - bi;
> + if (ai < bi) {
> + di = 0;
> + }
> + *(uint64_t *)(d + i) = di;
> + }
> + clear_high(d, oprsz, desc);
> +}
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 027f3e9740..f621422646 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1308,6 +1308,98 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
> }
>
> +void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
> +{
> + static const GVecGen3 g[4] = {
> + { .fno = gen_helper_gvec_ssadd8, .vece = MO_8 },
> + { .fno = gen_helper_gvec_ssadd16, .vece = MO_16 },
> + { .fno = gen_helper_gvec_ssadd32, .vece = MO_32 },
> + { .fno = gen_helper_gvec_ssadd64, .vece = MO_64 }
> + };
> + tcg_debug_assert(vece <= MO_64);
> + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
> +}
> +
> +void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
> +{
> + static const GVecGen3 g[4] = {
> + { .fno = gen_helper_gvec_sssub8, .vece = MO_8 },
> + { .fno = gen_helper_gvec_sssub16, .vece = MO_16 },
> + { .fno = gen_helper_gvec_sssub32, .vece = MO_32 },
> + { .fno = gen_helper_gvec_sssub64, .vece = MO_64 }
> + };
> + tcg_debug_assert(vece <= MO_64);
> + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
> +}
> +
> +static void tcg_gen_vec_usadd32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
> +{
> + TCGv_i32 max = tcg_const_i32(-1);
> + tcg_gen_add_i32(d, a, b);
> + tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d);
> + tcg_temp_free_i32(max);
> +}
> +
> +static void tcg_gen_vec_usadd32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
> +{
> + TCGv_i64 max = tcg_const_i64(-1);
> + tcg_gen_add_i64(d, a, b);
> + tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d);
> + tcg_temp_free_i64(max);
> +}
> +
> +void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
> +{
> + static const GVecGen3 g[4] = {
> + { .fno = gen_helper_gvec_usadd8, .vece = MO_8 },
> + { .fno = gen_helper_gvec_usadd16, .vece = MO_16 },
> + { .fni4 = tcg_gen_vec_usadd32_i32,
> + .fno = gen_helper_gvec_usadd32,
> + .vece = MO_32 },
> + { .fni8 = tcg_gen_vec_usadd32_i64,
> + .fno = gen_helper_gvec_usadd64,
> + .vece = MO_64 }
> + };
> + tcg_debug_assert(vece <= MO_64);
> + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
> +}
> +
> +static void tcg_gen_vec_ussub32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
> +{
> + TCGv_i32 min = tcg_const_i32(0);
> + tcg_gen_sub_i32(d, a, b);
> + tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d);
> + tcg_temp_free_i32(min);
> +}
> +
> +static void tcg_gen_vec_ussub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
> +{
> + TCGv_i64 min = tcg_const_i64(0);
> + tcg_gen_sub_i64(d, a, b);
> + tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d);
> + tcg_temp_free_i64(min);
> +}
> +
> +void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
> +{
> + static const GVecGen3 g[4] = {
> + { .fno = gen_helper_gvec_ussub8, .vece = MO_8 },
> + { .fno = gen_helper_gvec_ussub16, .vece = MO_16 },
> + { .fni4 = tcg_gen_vec_ussub32_i32,
> + .fno = gen_helper_gvec_ussub32,
> + .vece = MO_32 },
> + { .fni8 = tcg_gen_vec_ussub32_i64,
> + .fno = gen_helper_gvec_ussub64,
> + .vece = MO_64 }
> + };
> + tcg_debug_assert(vece <= MO_64);
> + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
> +}
> +
> /* Perform a vector negation using normal negation and a mask.
> Compare gen_subv_mask above. */
> static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
--
Alex Bennée
next prev parent reply other threads:[~2018-02-06 11:03 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-26 4:57 [Qemu-devel] [PATCH v11 00/20] tcg: generic vector operations Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 01/20] tcg: Allow multiple word entries into the constant pool Richard Henderson
2018-02-06 8:51 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 02/20] tcg: Add types and basic operations for host vectors Richard Henderson
2018-02-06 8:53 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 03/20] tcg: Standardize integral arguments to expanders Richard Henderson
2018-02-06 8:57 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 04/20] tcg: Add generic vector expanders Richard Henderson
2018-02-06 10:59 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 05/20] tcg: Add generic vector ops for constant shifts Richard Henderson
2018-02-06 11:00 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 06/20] tcg: Add generic vector ops for comparisons Richard Henderson
2018-02-06 11:01 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 07/20] tcg: Add generic vector ops for multiplication Richard Henderson
2018-02-06 11:02 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 08/20] tcg: Add generic helpers for saturating arithmetic Richard Henderson
2018-02-06 11:03 ` Alex Bennée [this message]
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 09/20] tcg: Add generic vector helpers with a scalar operand Richard Henderson
2018-02-06 11:04 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 10/20] tcg/optimize: Handle vector opcodes during optimize Richard Henderson
2018-02-06 11:07 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 11/20] target/arm: Align vector registers Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 12/20] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 13/20] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
2018-02-06 11:08 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 14/20] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
2018-02-06 11:09 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 15/20] target/arm: Use vector infrastructure for aa64 constant shifts Richard Henderson
2018-02-05 11:14 ` Peter Maydell
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 16/20] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
2018-02-06 11:10 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 17/20] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
2018-02-06 11:11 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate Richard Henderson
2018-02-06 11:13 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 19/20] tcg/i386: Add vector operations Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 20/20] tcg/aarch64: " Richard Henderson
2018-02-06 11:15 ` Alex Bennée
2018-01-26 17:25 ` [Qemu-devel] [PATCH v11 00/20] tcg: generic " no-reply
2018-02-06 11:24 ` Alex Bennée
2018-02-06 12:07 ` Philippe Mathieu-Daudé
2018-02-06 12:36 ` Alex Bennée
2018-02-06 16:24 ` Alex Bennée
2018-02-06 20:57 ` Alex Bennée
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