[Qemu-devel] Any topics for today's MTTCG sync-up call?

["Alex Bennée" <alex.bennee@linaro.org>]

Hi,

It's been a while since we've actually held the call. Here are some
things that might be worth discussing:

Soft Freeze
===========

This cycles soft-freeze is upon us. QHT has already been merged this
cycle which is a win. I've taken some of the lock contention patches
from my base enabling patches which improve the situation for linux-user
mode which I hope to get accepted this cycle (as they have been on the
list before and just need minor tweaks).

Are there any other patches that meet the soft-freeze criteria worth
trying to merge this cycle?

Quiescent Work
==============

Sergey has posted a series of patches that attempt to draw together all
the requirements of the various safe work patches into a common feature
that can be meet all the various use cases we have. It comes with a
thread safe tb_flush implementation although obviously there are other
uses in LL/SC and system emulation tasks. Is everyone happy with the
features it provides?

Atomics
=======

Emilio has posted his set of patches for implementing atomics in a
thread safe manner. So far I've only had a chance to glance over it but
it certainly has some interesting numbers. I suspect the next step will
be some serious benmarking between this and Alvise's upcoming re-base to
solve the race between an initial LL and the flushing of the TLB
entries.

As I understand it the LL/SC work will require some quiescent work to
complete before things can continue in a race free manner. The question
is if this cost is too high compared to Emilio's solution which suffers
from ABA but for practical purposes should be fine.

My intention is to build trees of both solutions on top of the base
patches and compare their performances on both real-world and artificial
work-loads.

Memory Ordering
===============

Pranith has posted a series of patches to the list the implement basic
memory ordering TCGOps. The current discussions centre mainly around the
best way to represent Acq/Rel semantics in an efficient manner.

Base-enabling patches
=====================

Since the posting of v3 I've had some feedback so I'll be update v4
while the other trees get reviewed before trying to build another
complete series (probably ARM based) and doing some benchmarking of the
system performance.

Any other topics that need discussion?

--
Alex Bennée