From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41047) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6GmJ-0000dz-RW for qemu-devel@nongnu.org; Tue, 08 Dec 2015 06:49:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a6GmG-0005c8-Kr for qemu-devel@nongnu.org; Tue, 08 Dec 2015 06:49:55 -0500 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]:34009) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a6GmG-0005bu-Al for qemu-devel@nongnu.org; Tue, 08 Dec 2015 06:49:52 -0500 Received: by wmvv187 with SMTP id v187so209827608wmv.1 for ; Tue, 08 Dec 2015 03:49:51 -0800 (PST) References: <1447345251-22625-1-git-send-email-alex.bennee@linaro.org> <1447345251-22625-4-git-send-email-alex.bennee@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Tue, 08 Dec 2015 11:49:49 +0000 Message-ID: <87r3ixp3c2.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v9 3/6] target-arm: kvm - support for single step List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: kvm-devel , Marc Zyngier , QEMU Developers , qemu-arm@nongnu.org, Christoffer Dall , Zhichao Huang , Paolo Bonzini , "kvmarm@lists.cs.columbia.edu" , arm-mail-list Peter Maydell writes: > On 12 November 2015 at 16:20, Alex Benn=C3=A9e w= rote: >> This adds support for single-step. There isn't much to do on the QEMU >> side as after we set-up the request for single step via the debug ioctl >> it is all handled within the kernel. >> >> Signed-off-by: Alex Benn=C3=A9e >> >> --- >> v2 >> - convert to using HSR_EC >> v3 >> - use internals.h definitions >> --- >> target-arm/kvm.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/target-arm/kvm.c b/target-arm/kvm.c >> index 50f70ef..d505a7e 100644 >> --- a/target-arm/kvm.c >> +++ b/target-arm/kvm.c >> @@ -535,6 +535,13 @@ static int kvm_handle_debug(CPUState *cs, struct kv= m_run *run) >> kvm_cpu_synchronize_state(cs); >> >> switch (hsr_ec) { >> + case EC_SOFTWARESTEP: >> + if (cs->singlestep_enabled) { >> + return true; >> + } else { >> + error_report("Came out of SINGLE STEP when not enabled"); >> + } >> + break; >> case EC_AA64_BKPT: >> if (kvm_find_sw_breakpoint(cs, env->pc)) { >> return true; >> @@ -595,6 +602,9 @@ int kvm_arch_on_sigbus(int code, void *addr) >> >> void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *= dbg) >> { >> + if (cs->singlestep_enabled) { >> + dbg->control |=3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP; >> + } > > Doesn't kvm_update_guest_debug() already set these bits, or am > I misreading it? Yeah. This raises an interesting problem about what to do when we don't have the capability. I could suppress those bits in the update function but that seems a bit hacky. Looking at the GDB capability code there doesn't seem to report breakpoint capability short of just failing when you try to set one. > >> if (kvm_sw_breakpoints_active(cs)) { >> dbg->control |=3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; >> } >> -- >> 2.6.3 > > thanks > -- PMM -- Alex Benn=C3=A9e