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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Thu, 01 May 2014 10:02:15 +0100
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Subject: Re: [Qemu-devel] [PATCH v1 2/4] target-arm: A64: Handle blr lr
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To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org


Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> For linked branches, updates to the link register happen
> conceptually after the read of the branch target register.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

I'm trying to think of a case where this could actually cause a problem
but I can't. However from a clarity/correctness point of view it's
better.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target-arm/translate-a64.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index d86b8ff..0862e54 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -1507,8 +1507,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
>      switch (opc) {
>      case 0: /* BR */
>      case 2: /* RET */
> +        tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
>          break;
>      case 1: /* BLR */
> +        tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
>          tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
>          break;
>      case 4: /* ERET */
> @@ -1527,7 +1529,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
>          return;
>      }
>  
> -    tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
>      s->is_jmp = DISAS_JUMP;
>  }

-- 
Alex Bennée