From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33702) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UpzzZ-00081X-Pa for qemu-devel@nongnu.org; Fri, 21 Jun 2013 07:59:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UpzzY-0000Ze-Ns for qemu-devel@nongnu.org; Fri, 21 Jun 2013 07:59:01 -0400 Received: from e37.co.us.ibm.com ([32.97.110.158]:33759) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UpzzY-0000ZX-H4 for qemu-devel@nongnu.org; Fri, 21 Jun 2013 07:59:00 -0400 Received: from /spool/local by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 21 Jun 2013 05:58:59 -0600 From: Anthony Liguori In-Reply-To: <51C4307F.7030201@ozlabs.ru> References: <1371806575-19347-1-git-send-email-aik@ozlabs.ru> <1371806575-19347-2-git-send-email-aik@ozlabs.ru> <37E1A8FA-6BFA-48D1-AA3E-118671C8638A@suse.de> <51C4307F.7030201@ozlabs.ru> Date: Fri, 21 Jun 2013 06:58:49 -0500 Message-ID: <87r4fvptdy.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 1/3] spapr pci msi: rework List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , Alexander Graf Cc: Alex Williamson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Alexey Kardashevskiy writes: > On 06/21/2013 08:31 PM, Alexander Graf wrote: >> >> On 21.06.2013, at 11:22, Alexey Kardashevskiy wrote: >> >>> Previously every PCI host bridge implemented its own MSI memory window >>> in order to catch msi_notify()/msix_notify() calls from various QEMU >>> MSI-capable devives such as virtio-pci or vfio and redirect them to >>> the guest via qemu_pulse_irq(). >> >> That's how hardware works, no? >> >>> >>> The encoded MSIMessage used to be encoded as: >>> * .addr - address in a MSI window, this is how QEMU knows which PHB >>> is the message for; >>> * .data - number of a device on a specific PHB and vector number. >>> >>> As a PHB has a destriptor for every device, and every descriptor has >>> first IRQ number and the number of IRQs, it can calculate global IRQ >>> number to use in qemu_pulse_irq(). >> >> How does this work on real hardware? > > > I do not understand the question, really. Here we are emulating pHyp which > is not real hardware and never pretended to be. Our guests do not touch MSI > records in the config space and use RTAS MSI calls instead. But RTAS is implemented as guest code. I suspect it's doing region access to generate the actual MSI events. Regards, Anthony Liguori > > >> >> >> Alex >> >>> However the total number of IRQs is not really big (at the moment it is >>> 1024 IRQs which start from 4096) and the existing system looks overdesigned. >>> The patch simplifies it. Specifically: >>> >>> 1. MSI windows were removed from PHB. >>> 2. Added one memory region for all MSIs. >>> 3. Now MSIMessage::addr is a number of first IRQ of a device, >>> MSIMessage:data is a number of a vector. >>> >>> Putting IRQ number to .data and not using .addr would make it even simpler >>> for MSI-X but it will not work for MSI with multiple vectors unless a first >>> IRQ number of a device is aligned to the MSI vectors number. >>> >>> The simplified scheme also allows easier MSIMessage->IRQ translation >>> for upcoming IRQFD support. >>> >>> Signed-off-by: Alexey Kardashevskiy >> > > > -- > Alexey