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Wed, 10 Dec 2025 03:00:03 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a82d414basm36783385e9.10.2025.12.10.03.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 03:00:02 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 1D6E45F814; Wed, 10 Dec 2025 11:00:02 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Michael Tokarev Cc: qemu-devel@nongnu.org, Jessica Clarke , Peter Maydell , "open list:ARM TCG CPUs" , qemu-stable Subject: Re: [PATCH v3] target/arm: handle unaligned PC during tlb probe In-Reply-To: <836d2623-6b79-4303-a34b-12e72c674822@tls.msk.ru> (Michael Tokarev's message of "Wed, 10 Dec 2025 13:14:42 +0300") References: <20251204203540.1381896-1-alex.bennee@linaro.org> <836d2623-6b79-4303-a34b-12e72c674822@tls.msk.ru> User-Agent: mu4e 1.12.14-pre3; emacs 30.1 Date: Wed, 10 Dec 2025 11:00:02 +0000 Message-ID: <87sedivbyl.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Michael Tokarev writes: > On 12/4/25 23:35, Alex Benn=C3=A9e wrote: >> PC alignment faults have priority over instruction aborts and we have >> code to deal with this in the translation front-ends. However during >> tb_lookup we can see a potentially faulting probe which doesn't get a >> MemOp set. If the page isn't available this results in >> EC_INSNABORT (0x20) instead of EC_PCALIGNMENT (0x22). >> As there is no easy way to set the appropriate MemOp in the >> instruction fetch probe path lets just detect it in >> arm_cpu_tlb_fill_align() ahead of the main alignment check. We also >> teach arm_deliver_fault to deliver the right syndrome for >> MMU_INST_FETCH alignment issues. >> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/3233 >> Tested-by: Jessica Clarke >> Signed-off-by: Alex Benn=C3=A9e > > This feels like a qemu-stable material (for all active stable > branches). By all means - its pretty self-contained. > > I'm picking it up for 10.0.x and 10.1.x. Please let me know > if I shouldn't. > > Thanks, > > /mjt --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro