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Mon, 27 Jun 2022 09:50:06 +0100 (BST) References: <20220607204557.658541-1-richard.henderson@linaro.org> <20220607204557.658541-25-richard.henderson@linaro.org> User-agent: mu4e 1.7.27; emacs 28.1.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org Subject: Re: [PATCH v4 24/53] semihosting: Split out common-semi-target.h Date: Mon, 27 Jun 2022 09:48:21 +0100 In-reply-to: <20220607204557.658541-25-richard.henderson@linaro.org> Message-ID: <87sfnqlcch.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Move the ARM and RISCV specific helpers into > their own header file. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/common-semi-target.h | 62 ++++++++++++++++++++ > target/riscv/common-semi-target.h | 50 ++++++++++++++++ > semihosting/arm-compat-semi.c | 94 +------------------------------ > 3 files changed, 113 insertions(+), 93 deletions(-) > create mode 100644 target/arm/common-semi-target.h > create mode 100644 target/riscv/common-semi-target.h > > diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-tar= get.h > new file mode 100644 > index 0000000000..629d75ca5a > --- /dev/null > +++ b/target/arm/common-semi-target.h > @@ -0,0 +1,62 @@ > +/* > + * Target-specific parts of semihosting/arm-compat-semi.c. > + * > + * Copyright (c) 2005, 2007 CodeSourcery. > + * Copyright (c) 2019, 2022 Linaro > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H > +#define TARGET_ARM_COMMON_SEMI_TARGET_H > + > +#ifndef CONFIG_USER_ONLY > +#include "hw/arm/boot.h" > +#endif > + > +static inline target_ulong common_semi_arg(CPUState *cs, int argno) > +{ > + ARMCPU *cpu =3D ARM_CPU(cs); > + CPUARMState *env =3D &cpu->env; > + if (is_a64(env)) { > + return env->xregs[argno]; > + } else { > + return env->regs[argno]; > + } > +} > + > +static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) > +{ > + ARMCPU *cpu =3D ARM_CPU(cs); > + CPUARMState *env =3D &cpu->env; > + if (is_a64(env)) { > + env->xregs[0] =3D ret; > + } else { > + env->regs[0] =3D ret; > + } > +} > + > +static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) > +{ > + return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); > +} > + > +static inline bool is_64bit_semihosting(CPUArchState *env) > +{ > + return is_a64(env); > +} > + > +static inline target_ulong common_semi_stack_bottom(CPUState *cs) > +{ > + ARMCPU *cpu =3D ARM_CPU(cs); > + CPUARMState *env =3D &cpu->env; > + return is_a64(env) ? env->xregs[31] : env->regs[13]; > +} > + > +static inline bool common_semi_has_synccache(CPUArchState *env) > +{ > + /* Ok for A64, invalid for A32/T32 */ > + return is_a64(env); > +} > + > +#endif > diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi= -target.h > new file mode 100644 > index 0000000000..7c8a59e0cc > --- /dev/null > +++ b/target/riscv/common-semi-target.h > @@ -0,0 +1,50 @@ > +/* > + * Target-specific parts of semihosting/arm-compat-semi.c. > + * > + * Copyright (c) 2005, 2007 CodeSourcery. > + * Copyright (c) 2019, 2022 Linaro > + * Copyright =C2=A9 2020 by Keith Packard > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H > +#define TARGET_RISCV_COMMON_SEMI_TARGET_H > + > +static inline target_ulong common_semi_arg(CPUState *cs, int argno) > +{ > + RISCVCPU *cpu =3D RISCV_CPU(cs); > + CPURISCVState *env =3D &cpu->env; > + return env->gpr[xA0 + argno]; > +} > + > +static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) > +{ > + RISCVCPU *cpu =3D RISCV_CPU(cs); > + CPURISCVState *env =3D &cpu->env; > + env->gpr[xA0] =3D ret; > +} > + > +static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) > +{ > + return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) = =3D=3D 8); > +} > + > +static inline bool is_64bit_semihosting(CPUArchState *env) > +{ > + return riscv_cpu_mxl(env) !=3D MXL_RV32; > +} > + > +static inline target_ulong common_semi_stack_bottom(CPUState *cs) > +{ > + RISCVCPU *cpu =3D RISCV_CPU(cs); > + CPURISCVState *env =3D &cpu->env; > + return env->gpr[xSP]; > +} > + > +static inline bool common_semi_has_synccache(CPUArchState *env) > +{ > + return true; > +} > + > +#endif > diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c > index 50f40a2a1a..5e442e549d 100644 > --- a/semihosting/arm-compat-semi.c > +++ b/semihosting/arm-compat-semi.c > @@ -46,9 +46,6 @@ > #else > #include "qemu/cutils.h" > #include "hw/loader.h" > -#ifdef TARGET_ARM > -#include "hw/arm/boot.h" > -#endif > #include "hw/boards.h" > #endif >=20=20 > @@ -182,96 +179,7 @@ static LayoutInfo common_semi_find_bases(CPUState *c= s) >=20=20 > #endif >=20=20 > -#ifdef TARGET_ARM > -static inline target_ulong > -common_semi_arg(CPUState *cs, int argno) > -{ > - ARMCPU *cpu =3D ARM_CPU(cs); > - CPUARMState *env =3D &cpu->env; > - if (is_a64(env)) { > - return env->xregs[argno]; > - } else { > - return env->regs[argno]; > - } > -} > - > -static inline void > -common_semi_set_ret(CPUState *cs, target_ulong ret) > -{ > - ARMCPU *cpu =3D ARM_CPU(cs); > - CPUARMState *env =3D &cpu->env; > - if (is_a64(env)) { > - env->xregs[0] =3D ret; > - } else { > - env->regs[0] =3D ret; > - } > -} > - > -static inline bool > -common_semi_sys_exit_extended(CPUState *cs, int nr) > -{ > - return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); > -} > - > -static inline bool is_64bit_semihosting(CPUArchState *env) > -{ > - return is_a64(env); > -} > - > -static inline target_ulong common_semi_stack_bottom(CPUState *cs) > -{ > - ARMCPU *cpu =3D ARM_CPU(cs); > - CPUARMState *env =3D &cpu->env; > - return is_a64(env) ? env->xregs[31] : env->regs[13]; > -} > - > -static inline bool common_semi_has_synccache(CPUArchState *env) > -{ > - /* Ok for A64, invalid for A32/T32. */ > - return is_a64(env); > -} > -#endif /* TARGET_ARM */ > - > -#ifdef TARGET_RISCV > -static inline target_ulong > -common_semi_arg(CPUState *cs, int argno) > -{ > - RISCVCPU *cpu =3D RISCV_CPU(cs); > - CPURISCVState *env =3D &cpu->env; > - return env->gpr[xA0 + argno]; > -} > - > -static inline void > -common_semi_set_ret(CPUState *cs, target_ulong ret) > -{ > - RISCVCPU *cpu =3D RISCV_CPU(cs); > - CPURISCVState *env =3D &cpu->env; > - env->gpr[xA0] =3D ret; > -} > - > -static inline bool > -common_semi_sys_exit_extended(CPUState *cs, int nr) > -{ > - return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) = =3D=3D 8); > -} > - > -static inline bool is_64bit_semihosting(CPUArchState *env) > -{ > - return riscv_cpu_mxl(env) !=3D MXL_RV32; > -} > - > -static inline target_ulong common_semi_stack_bottom(CPUState *cs) > -{ > - RISCVCPU *cpu =3D RISCV_CPU(cs); > - CPURISCVState *env =3D &cpu->env; > - return env->gpr[xSP]; > -} > - > -static inline bool common_semi_has_synccache(CPUArchState *env) > -{ > - return true; > -} > -#endif > +#include "common-semi-target.h" >=20=20 > /* > * The semihosting API has no concept of its errno being thread-safe, --=20 Alex Benn=C3=A9e