From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wfmoe-0002r9-56 for qemu-devel@nongnu.org; Thu, 01 May 2014 04:58:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WfmoZ-0006Nq-H6 for qemu-devel@nongnu.org; Thu, 01 May 2014 04:58:04 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:40111 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfmoZ-0006NV-Al for qemu-devel@nongnu.org; Thu, 01 May 2014 04:57:59 -0400 References: <1398926097-28097-1-git-send-email-edgar.iglesias@gmail.com> <1398926097-28097-4-git-send-email-edgar.iglesias@gmail.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1398926097-28097-4-git-send-email-edgar.iglesias@gmail.com> Date: Thu, 01 May 2014 09:59:08 +0100 Message-ID: <87siotri1v.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v1 3/4] target-arm: A64: Fix a typo whendeclaring TLBI opss List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" > > Harmless typo as opc1 defaults to zero and opc2 gets > re-declared to its correct value. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée > --- > target-arm/helper.c | 24 ++++++++++++------------ > 1 file changed, 12 insertions(+), 12 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 330bfc7..0b8e8aa 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1893,51 +1893,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .access = PL1_W, .type = ARM_CP_NOP }, > /* TLBI operations */ > { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbiall_write }, > { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_va_write }, > { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_asid_write }, > { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_vaa_write }, > { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_va_write }, > { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_vaa_write }, > { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbiall_write }, > { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_va_write }, > { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_asid_write }, > { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_vaa_write }, > { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_va_write }, > { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, > - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7, > + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, > .access = PL1_W, .type = ARM_CP_NO_MIGRATE, > .writefn = tlbi_aa64_vaa_write }, > #ifndef CONFIG_USER_ONLY -- Alex Bennée