* [RFC PATCH v2 0/2] Implement Power ISA 3.1B hash insns
@ 2022-07-11 13:42 Víctor Colombo
2022-07-11 13:42 ` [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk Víctor Colombo
2022-07-11 13:42 ` [RFC PATCH v2 2/2] target/ppc: Implement hashstp and hashchkp Víctor Colombo
0 siblings, 2 replies; 5+ messages in thread
From: Víctor Colombo @ 2022-07-11 13:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
mst, cohuck, pbonzini, farosas
This patch series implements the 4 instructions added in Power ISA
3.1B:
- hashchk
- hashst
- hashchkp
- hashstp
What do you think about the choice to implement the hash algorithm
from the ground up, following the SIMON-like algorithm presented in
Power ISA? IIUC, this algorithm is not the same as the original[1].
Other options would be to use other algorithm already implemented
in QEMU, or even make this instruction a nop for all Power versions.
Also, I was thinking about using the call to spr_register_kvm() in
init_proc_POWER10 to initialize the registers with a random value.
I'm not sure what is the behavior here, I would expect that is the job
of the OS to set the regs, but looks like KVM is not exporting them,
so they are always 0 (?). Does anyone have any insight on this?
v1->v2:
- Split the patch in 2
- Rebase to master
[1] https://eprint.iacr.org/2013/404.pdf
Víctor Colombo (2):
target/ppc: Implement hashst and hashchk instructions
target/ppc: Implement hashstp and hashchkp
linux-headers/asm-powerpc/kvm.h | 3 +
target/ppc/cpu.h | 2 +
target/ppc/cpu_init.c | 7 ++
target/ppc/excp_helper.c | 82 ++++++++++++++++++++++
target/ppc/helper.h | 4 ++
target/ppc/insn32.decode | 10 +++
target/ppc/translate.c | 5 ++
target/ppc/translate/fixedpoint-impl.c.inc | 34 +++++++++
8 files changed, 147 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk
2022-07-11 13:42 [RFC PATCH v2 0/2] Implement Power ISA 3.1B hash insns Víctor Colombo
@ 2022-07-11 13:42 ` Víctor Colombo
2022-07-11 14:18 ` Cornelia Huck
2022-07-11 13:42 ` [RFC PATCH v2 2/2] target/ppc: Implement hashstp and hashchkp Víctor Colombo
1 sibling, 1 reply; 5+ messages in thread
From: Víctor Colombo @ 2022-07-11 13:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
mst, cohuck, pbonzini, farosas
Implementation for instructions hashst and hashchk, which were added
in Power ISA 3.1B.
It was decided to implement the hash algorithm from ground up in this
patch exactly as described in Power ISA.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
| 2 +
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 4 ++
target/ppc/excp_helper.c | 80 ++++++++++++++++++++++
target/ppc/helper.h | 2 +
target/ppc/insn32.decode | 8 +++
target/ppc/translate.c | 5 ++
target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++
8 files changed, 134 insertions(+)
--git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 9f18fa090f..dd58d574bf 100644
--- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -646,6 +646,8 @@ struct kvm_ppc_cpu_char {
#define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
#define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
#define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
+/* FIXME: KVM hasn't exposed these registers yet */
+#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
/* Transactional Memory checkpointed state:
* This is all GPRs, all VSX regs and a subset of SPRs
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 7aaff9dcc5..f3f98d7a01 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1677,6 +1677,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
#define SPR_PTCR (0x1D0)
+#define SPR_POWER_HASHKEYR (0x1D4)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 86ad28466a..db541c531a 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6490,6 +6490,10 @@ static void init_proc_POWER10(CPUPPCState *env)
spr_read_generic, spr_write_generic,
KVM_REG_PPC_PSSCR, 0);
+ spr_register_kvm(env, SPR_POWER_HASHKEYR, "HASHKEYR",
+ SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_HASHKEYR, 0x0);
+
/* env variables */
env->dcache_line_size = 128;
env->icache_line_size = 128;
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index cb752b184a..34893bdf9f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2174,6 +2174,86 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
#endif
#endif
+static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
+{
+ const uint16_t c = 0xfffc;
+ const uint64_t z0 = 0xfa2561cdf44ac398ULL;
+ uint16_t z = 0, temp;
+ uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32];
+
+ for (int i = 3; i >= 0; i--) {
+ k[i] = key & 0xffff;
+ key >>= 16;
+ }
+ xleft[0] = x & 0xffff;
+ xright[0] = (x >> 16) & 0xffff;
+
+ for (int i = 0; i < 28; i++) {
+ z = (z0 >> (63 - i)) & 1;
+ temp = ror16(k[i + 3], 3) ^ k[i + 1];
+ k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1);
+ }
+
+ for (int i = 0; i < 8; i++) {
+ eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)];
+ eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)];
+ eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)];
+ eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)];
+ }
+
+ for (int i = 0; i < 32; i++) {
+ fxleft[i] = (rol16(xleft[i], 1) &
+ rol16(xleft[i], 8)) ^ rol16(xleft[i], 2);
+ xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i];
+ xright[i + 1] = xleft[i];
+ }
+
+ return (((uint32_t)xright[32]) << 16) | xleft[32];
+}
+
+static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
+{
+ uint64_t stage0_h = 0ULL, stage0_l = 0ULL;
+ uint64_t stage1_h, stage1_l;
+
+ for (int i = 0; i < 4; i++) {
+ stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1));
+ stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i);
+ stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1));
+ stage0_l |= (ra & 0xff) << (8 * 2 * i);
+ rb >>= 8;
+ ra >>= 8;
+ }
+
+ stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32;
+ stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1);
+ stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32;
+ stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3);
+
+ return stage1_h ^ stage1_l;
+}
+
+#define HELPER_HASH(op, key, store) \
+void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
+ target_ulong rb) \
+{ \
+ uint64_t chash = hash_digest(ra, rb, key), lhash; \
+ \
+ if (store) { \
+ cpu_stq_data_ra(env, ea, chash, GETPC()); \
+ } else { \
+ lhash = cpu_ldq_data_ra(env, ea, GETPC()); \
+ if (lhash != chash) { \
+ /* hashes don't match, trap */ \
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, \
+ POWERPC_EXCP_TRAP, GETPC()); \
+ } \
+ } \
+}
+
+HELPER_HASH(HASHST, env->spr[SPR_POWER_HASHKEYR], true)
+HELPER_HASH(HASHCHK, env->spr[SPR_POWER_HASHKEYR], false)
+
#if !defined(CONFIG_USER_ONLY)
#ifdef CONFIG_TCG
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ed0641a234..84447aa3a5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -4,6 +4,8 @@ DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#endif
+DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
+DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_2(store_msr, void, env, tl)
DEF_HELPER_1(rfi, void, env)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f7653ef9d5..23e8f56f82 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -163,6 +163,9 @@
@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
@X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
+%x_dw 0:1 21:5 !function=dw_compose_ea
+@X_DW ...... ..... ra:5 rb:5 .......... . &X rt=%x_dw
+
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -314,6 +317,11 @@ CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
PEXTD 011111 ..... ..... ..... 0010111100 - @X
+# Fixed-Point Hash Instructions
+
+HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
+HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
+
## BCD Assist
ADDG6S 011111 ..... ..... ..... - 001001010 - @X
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1d6daa4608..1a049564d6 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6578,6 +6578,11 @@ static int times_16(DisasContext *ctx, int x)
return x * 16;
}
+static int64_t dw_compose_ea(DisasContext *ctx, int x)
+{
+ return deposit64(0xfffffffffffffe00, 3, 6, x);
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index cb0097bedb..f525144398 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -543,3 +543,35 @@ static bool trans_CBCDTD(DisasContext *ctx, arg_X_sa *a)
gen_helper_CBCDTD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
return true;
}
+
+static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
+ void (*helper)(TCGv_ptr, TCGv, TCGv, TCGv))
+{
+ TCGv ea;
+
+ if (!(ctx->insns_flags2 & PPC2_ISA310)) {
+ /* if version is before v3.1, this operation is a nop */
+ return true;
+ }
+
+ if (priv) {
+ /* if instruction is privileged but the context is in user space */
+ REQUIRE_SV(ctx);
+ }
+
+ if (unlikely(a->ra == 0)) {
+ /* if RA=0, the instruction form is invalid */
+ gen_invalid(ctx);
+ return true;
+ }
+
+ ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
+ helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
+
+ tcg_temp_free(ea);
+
+ return true;
+}
+
+TRANS(HASHST, do_hash, false, gen_helper_HASHST)
+TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RFC PATCH v2 2/2] target/ppc: Implement hashstp and hashchkp
2022-07-11 13:42 [RFC PATCH v2 0/2] Implement Power ISA 3.1B hash insns Víctor Colombo
2022-07-11 13:42 ` [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk Víctor Colombo
@ 2022-07-11 13:42 ` Víctor Colombo
1 sibling, 0 replies; 5+ messages in thread
From: Víctor Colombo @ 2022-07-11 13:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
mst, cohuck, pbonzini, farosas
Implementation for instructions hashstp and hashchkp, the privileged
versions of hashst and hashchk, which were added in Power ISA 3.1B.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
| 1 +
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 3 +++
target/ppc/excp_helper.c | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode | 2 ++
target/ppc/translate/fixedpoint-impl.c.inc | 2 ++
7 files changed, 13 insertions(+)
--git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index dd58d574bf..4ae4718143 100644
--- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -648,6 +648,7 @@ struct kvm_ppc_cpu_char {
#define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
/* FIXME: KVM hasn't exposed these registers yet */
#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
+#define KVM_REG_PPC_HASHPKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
/* Transactional Memory checkpointed state:
* This is all GPRs, all VSX regs and a subset of SPRs
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f3f98d7a01..e6fc9c41f0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1678,6 +1678,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_TIR (0x1BE)
#define SPR_PTCR (0x1D0)
#define SPR_POWER_HASHKEYR (0x1D4)
+#define SPR_POWER_HASHPKEYR (0x1D5)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index db541c531a..ea3197c2be 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6493,6 +6493,9 @@ static void init_proc_POWER10(CPUPPCState *env)
spr_register_kvm(env, SPR_POWER_HASHKEYR, "HASHKEYR",
SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,
KVM_REG_PPC_HASHKEYR, 0x0);
+ spr_register_kvm(env, SPR_POWER_HASHPKEYR, "HASHPKEYR",
+ SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_HASHPKEYR, 0x0);
/* env variables */
env->dcache_line_size = 128;
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 34893bdf9f..0998e8374e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2253,6 +2253,8 @@ void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
HELPER_HASH(HASHST, env->spr[SPR_POWER_HASHKEYR], true)
HELPER_HASH(HASHCHK, env->spr[SPR_POWER_HASHKEYR], false)
+HELPER_HASH(HASHSTP, env->spr[SPR_POWER_HASHPKEYR], true)
+HELPER_HASH(HASHCHKP, env->spr[SPR_POWER_HASHPKEYR], false)
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 84447aa3a5..51a5910cb7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -6,6 +6,8 @@ DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#endif
DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
+DEF_HELPER_4(HASHSTP, void, env, tl, tl, tl)
+DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_2(store_msr, void, env, tl)
DEF_HELPER_1(rfi, void, env)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 23e8f56f82..6dfb6d5880 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -321,6 +321,8 @@ PEXTD 011111 ..... ..... ..... 0010111100 - @X
HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
+HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW
+HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
## BCD Assist
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index f525144398..c151c1fe46 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -575,3 +575,5 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
TRANS(HASHST, do_hash, false, gen_helper_HASHST)
TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
+TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP)
+TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP)
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk
2022-07-11 13:42 ` [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk Víctor Colombo
@ 2022-07-11 14:18 ` Cornelia Huck
2022-07-11 15:30 ` Víctor Colombo
0 siblings, 1 reply; 5+ messages in thread
From: Cornelia Huck @ 2022-07-11 14:18 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
mst, pbonzini, farosas
On Mon, Jul 11 2022, Víctor Colombo <victor.colombo@eldorado.org.br> wrote:
> Implementation for instructions hashst and hashchk, which were added
> in Power ISA 3.1B.
>
> It was decided to implement the hash algorithm from ground up in this
> patch exactly as described in Power ISA.
>
> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
> ---
> linux-headers/asm-powerpc/kvm.h | 2 +
> target/ppc/cpu.h | 1 +
> target/ppc/cpu_init.c | 4 ++
> target/ppc/excp_helper.c | 80 ++++++++++++++++++++++
> target/ppc/helper.h | 2 +
> target/ppc/insn32.decode | 8 +++
> target/ppc/translate.c | 5 ++
> target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++
> 8 files changed, 134 insertions(+)
>
> diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
> index 9f18fa090f..dd58d574bf 100644
> --- a/linux-headers/asm-powerpc/kvm.h
> +++ b/linux-headers/asm-powerpc/kvm.h
> @@ -646,6 +646,8 @@ struct kvm_ppc_cpu_char {
> #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
> #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
> #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
> +/* FIXME: KVM hasn't exposed these registers yet */
> +#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
>
> /* Transactional Memory checkpointed state:
> * This is all GPRs, all VSX regs and a subset of SPRs
<editorial>
Please split any header updates into a separate patch (a full header
update or, if the changes are not yet included in Linux, a placeholder
patch. Thank you :)
</editorial>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk
2022-07-11 14:18 ` Cornelia Huck
@ 2022-07-11 15:30 ` Víctor Colombo
0 siblings, 0 replies; 5+ messages in thread
From: Víctor Colombo @ 2022-07-11 15:30 UTC (permalink / raw)
To: Cornelia Huck, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, mst, pbonzini,
farosas
On 11/07/2022 11:18, Cornelia Huck wrote:
> On Mon, Jul 11 2022, Víctor Colombo <victor.colombo@eldorado.org.br> wrote:
>
>> Implementation for instructions hashst and hashchk, which were added
>> in Power ISA 3.1B.
>>
>> It was decided to implement the hash algorithm from ground up in this
>> patch exactly as described in Power ISA.
>>
>> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
>> ---
>> linux-headers/asm-powerpc/kvm.h | 2 +
>> target/ppc/cpu.h | 1 +
>> target/ppc/cpu_init.c | 4 ++
>> target/ppc/excp_helper.c | 80 ++++++++++++++++++++++
>> target/ppc/helper.h | 2 +
>> target/ppc/insn32.decode | 8 +++
>> target/ppc/translate.c | 5 ++
>> target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++
>> 8 files changed, 134 insertions(+)
>>
>> diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
>> index 9f18fa090f..dd58d574bf 100644
>> --- a/linux-headers/asm-powerpc/kvm.h
>> +++ b/linux-headers/asm-powerpc/kvm.h
>> @@ -646,6 +646,8 @@ struct kvm_ppc_cpu_char {
>> #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
>> #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
>> #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
>> +/* FIXME: KVM hasn't exposed these registers yet */
>> +#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
>>
>> /* Transactional Memory checkpointed state:
>> * This is all GPRs, all VSX regs and a subset of SPRs
>
> <editorial>
> Please split any header updates into a separate patch (a full header
> update or, if the changes are not yet included in Linux, a placeholder
> patch. Thank you :)
> </editorial>
>
Hello Cornelia
I'll do it. Thanks for your reply
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-07-11 15:37 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-07-11 13:42 [RFC PATCH v2 0/2] Implement Power ISA 3.1B hash insns Víctor Colombo
2022-07-11 13:42 ` [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk Víctor Colombo
2022-07-11 14:18 ` Cornelia Huck
2022-07-11 15:30 ` Víctor Colombo
2022-07-11 13:42 ` [RFC PATCH v2 2/2] target/ppc: Implement hashstp and hashchkp Víctor Colombo
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