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Mon, 11 Jul 2022 14:18:04 +0000 (UTC) Received: from localhost (unknown [10.39.192.23]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C7891492C3B; Mon, 11 Jul 2022 14:18:03 +0000 (UTC) From: Cornelia Huck To: =?utf-8?Q?V=C3=ADctor?= Colombo , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, victor.colombo@eldorado.org.br, mst@redhat.com, pbonzini@redhat.com, farosas@linux.ibm.com Subject: Re: [RFC PATCH v2 1/2] target/ppc: Implement hashst and hashchk In-Reply-To: <20220711134258.63147-2-victor.colombo@eldorado.org.br> Organization: Red Hat GmbH References: <20220711134258.63147-1-victor.colombo@eldorado.org.br> <20220711134258.63147-2-victor.colombo@eldorado.org.br> User-Agent: Notmuch/0.36 (https://notmuchmail.org) Date: Mon, 11 Jul 2022 16:18:02 +0200 Message-ID: <87tu7n68dh.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.85 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jul 11 2022, V=C3=ADctor Colombo w= rote: > Implementation for instructions hashst and hashchk, which were added > in Power ISA 3.1B. > > It was decided to implement the hash algorithm from ground up in this > patch exactly as described in Power ISA. > > Signed-off-by: V=C3=ADctor Colombo > --- > linux-headers/asm-powerpc/kvm.h | 2 + > target/ppc/cpu.h | 1 + > target/ppc/cpu_init.c | 4 ++ > target/ppc/excp_helper.c | 80 ++++++++++++++++++++++ > target/ppc/helper.h | 2 + > target/ppc/insn32.decode | 8 +++ > target/ppc/translate.c | 5 ++ > target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++ > 8 files changed, 134 insertions(+) > > diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/= kvm.h > index 9f18fa090f..dd58d574bf 100644 > --- a/linux-headers/asm-powerpc/kvm.h > +++ b/linux-headers/asm-powerpc/kvm.h > @@ -646,6 +646,8 @@ struct kvm_ppc_cpu_char { > #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) > #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) > #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) > +/* FIXME: KVM hasn't exposed these registers yet */ > +#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00) >=20=20 > /* Transactional Memory checkpointed state: > * This is all GPRs, all VSX regs and a subset of SPRs Please split any header updates into a separate patch (a full header update or, if the changes are not yet included in Linux, a placeholder patch. Thank you :)