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Fri, 14 Jan 2022 21:46:14 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CD7D0112062; Fri, 14 Jan 2022 21:46:13 +0000 (GMT) Received: from localhost (unknown [9.211.74.33]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTPS; Fri, 14 Jan 2022 21:46:13 +0000 (GMT) From: Fabiano Rosas To: David Gibson Subject: Re: [PATCH 2/8] target/ppc: 405: Add missing exception handlers In-Reply-To: References: <20220110181546.4131853-1-farosas@linux.ibm.com> <20220110181546.4131853-3-farosas@linux.ibm.com> Date: Fri, 14 Jan 2022 18:46:10 -0300 Message-ID: <87tue6vvml.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VtIHSEByvzhaUKv-UjDtVDl9e1OjxIQh X-Proofpoint-GUID: 1P_PlG00_wbb-inf1M9shn09Nd-FJU5L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-14_06,2022-01-14_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=979 impostorscore=0 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201140122 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" David Gibson writes: > On Mon, Jan 10, 2022 at 03:15:40PM -0300, Fabiano Rosas wrote: >> Signed-off-by: Fabiano Rosas >> --- >> target/ppc/cpu_init.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c >> index a50ddaeaae..9097948e67 100644 >> --- a/target/ppc/cpu_init.c >> +++ b/target/ppc/cpu_init.c >> @@ -1951,7 +1951,9 @@ static void init_excp_4xx_softmmu(CPUPPCState *env) >> env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; >> env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; >> env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; >> + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; > > I have a vague recollection from my days of working on 405 that there > may have been something funky with FP emulation on there: e.g. FP > instructions causing 0x700 program interrupts instead of FP unavailble > interrupts or something. Maybe this (from the manual): Program - causing conditions: Attempted execution of illegal instructions, TRAP instruction, privileged instruction in problem state, or auxiliary processor (APU) instruction, or unimplemented FPU instruction, or unimplemented APU instruction, or APU interrupt, or FPU interrupt FPU Unavailable - causing conditions: Attempted execution of an FPU instruction when MSR[FP]=0. There's also this bit: Attempted execution of an APU instruction while the APUc405exception signal is asserted) results in a program interrupt. Similarly, attempted execution of an FPU instruction whilethe FPUc405exception signal is asserted) also results in a program interrupt. The following also result in program interrupts: attempted execution of an APU instruction while APUc405DcdAPUOp is asserted but APUC405DcdValidOp is deasserted; and attempted execution of an FPU instruction while APUc405DcdFpuOp but APUC405DcdValidOp is deasserted. > I might be remembering incorrectly - the manual does seem to imply > that 0x800 FP unavailable is there as normal, but it might be worth > double checking this (against real hardware, if possible). The Linux kernel has the vectors that I'm adding disabled: EXCEPTION(0x0800, Trap_08, unknown_exception) <-- FPU EXCEPTION(0x0900, Trap_09, unknown_exception) EXCEPTION(0x0A00, Trap_0A, unknown_exception) EXCEPTION(0x0B00, Trap_0B, unknown_exception) ... EXCEPTION(0x0F00, Trap_0F, unknown_exception) <-- APU (0xf20 would probably cause a crash as we'd jump to the middle of the exception prologue) Maybe I should drop this patch then? That way future developers won't feel tempted to raise one of these. It seems mostly inconsequential either way, what do you think?