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Tue, 22 Jun 2021 18:52:07 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 15MIq6mu21299560 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 22 Jun 2021 18:52:06 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3C75C7805E; Tue, 22 Jun 2021 18:52:06 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A37F27805F; Tue, 22 Jun 2021 18:52:05 +0000 (GMT) Received: from localhost (unknown [9.211.80.241]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 22 Jun 2021 18:52:05 +0000 (GMT) From: Fabiano Rosas To: Greg Kurz , qemu-devel@nongnu.org Subject: Re: [PATCH 1/2] target/ppc: Introduce ppc_interrupts_little_endian() In-Reply-To: <20210622140926.677618-2-groug@kaod.org> References: <20210622140926.677618-1-groug@kaod.org> <20210622140926.677618-2-groug@kaod.org> Date: Tue, 22 Jun 2021 15:52:03 -0300 Message-ID: <87tulpohpo.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: OfC49Ys3Og6115W1tDC0XRzDY3EO77ZJ X-Proofpoint-GUID: OfC49Ys3Og6115W1tDC0XRzDY3EO77ZJ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-22_12:2021-06-22, 2021-06-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106220113 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_BL=0.001, RCVD_IN_MSPIKE_L3=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Greg Kurz writes: > PowerPC CPUs use big endian by default but starting with POWER7, > server grade CPUs use the ILE bit of the LPCR special purpose > register to decide on the endianness to use when handling > interrupts. This gives a clue to QEMU on the endianness the > guest kernel is running, which is needed when generating an > ELF dump of the guest or when delivering an FWNMI machine > check interrupt. > > Commit 382d2db62bcb ("target-ppc: Introduce callback for interrupt > endianness") added a class method to PowerPCCPUClass to modelize > this : default implementation returns a fixed "big endian" value, > while POWER7 and newer do the LPCR_ILE check. This is suboptimal > as it forces to implement the method for every new CPU family, and > it is very unlikely that this will ever be different than what we > have today. > > We basically only have three cases to consider: > a) CPU doesn't have an LPCR => big endian > b) CPU has an LPCR but doesn't support the ILE bit => big endian > c) CPU has an LPCR and supports the ILE bit => little or big endian > > Instead of class methods, introduce an inline helper that checks the > ILE bit in the LPCR_MASK to decide on the outcome. The new helper > words little endian instead of big endian. This allows to drop a ! > operator in ppc_cpu_do_fwnmi_machine_check(). > > Signed-off-by: Greg Kurz Reviewed-by: Fabiano Rosas > --- > target/ppc/cpu.h | 15 +++++++++++++++ > target/ppc/arch_dump.c | 8 +++----- > target/ppc/excp_helper.c | 3 +-- > 3 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index b4de0db7ff5c..93d308ac8f2d 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2643,6 +2643,21 @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr) > return cpu->env.spr_cb[spr].name != NULL; > } > > +static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu) > +{ > + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > + > + /* > + * Only models that have an LPCR and know about LPCR_ILE can do little > + * endian. > + */ > + if (pcc->lpcr_mask & LPCR_ILE) { > + return !!(cpu->env.spr[SPR_LPCR] & LPCR_ILE); > + } > + > + return false; > +} > + > void dump_mmu(CPUPPCState *env); > > void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); > diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c > index 9210e61ef463..bb392f6d8885 100644 > --- a/target/ppc/arch_dump.c > +++ b/target/ppc/arch_dump.c > @@ -227,22 +227,20 @@ int cpu_get_dump_info(ArchDumpInfo *info, > const struct GuestPhysBlockList *guest_phys_blocks) > { > PowerPCCPU *cpu; > - PowerPCCPUClass *pcc; > > if (first_cpu == NULL) { > return -1; > } > > cpu = POWERPC_CPU(first_cpu); > - pcc = POWERPC_CPU_GET_CLASS(cpu); > > info->d_machine = PPC_ELF_MACHINE; > info->d_class = ELFCLASS; > > - if ((*pcc->interrupts_big_endian)(cpu)) { > - info->d_endian = ELFDATA2MSB; > - } else { > + if (ppc_interrupts_little_endian(cpu)) { > info->d_endian = ELFDATA2LSB; > + } else { > + info->d_endian = ELFDATA2MSB; > } > /* 64KB is the max page size for pseries kernel */ > if (strncmp(object_get_typename(qdev_get_machine()), > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index fd147e2a3766..a79a0ed465e5 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -1099,7 +1099,6 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) > { > PowerPCCPU *cpu = POWERPC_CPU(cs); > CPUPPCState *env = &cpu->env; > - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > target_ulong msr = 0; > > /* > @@ -1108,7 +1107,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) > */ > msr = (1ULL << MSR_ME); > msr |= env->msr & (1ULL << MSR_SF); > - if (!(*pcc->interrupts_big_endian)(cpu)) { > + if (ppc_interrupts_little_endian(cpu)) { > msr |= (1ULL << MSR_LE); > }