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X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Create a function to compute the values of the TBFLAG_A32 bits > that will be cached, and are used by all profiles. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/helper.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 69da04786e..f05d042474 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMStat= e *env, int fp_el, > return flags; > } > > +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, > + ARMMMUIdx mmu_idx, uint32_t fla= gs) > +{ > + flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); > + flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); > + > + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); > +} > + > static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, > ARMMMUIdx mmu_idx) > { > @@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, > ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); > int current_el =3D arm_current_el(env); > int fp_el =3D fp_exception_el(env, current_el); > - uint32_t flags =3D 0; > + uint32_t flags; > > if (is_a64(env)) { > *pc =3D env->pc; > @@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, tar= get_ulong *pc, > } > } else { > *pc =3D env->regs[15]; > + flags =3D rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); > flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); > flags =3D FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len= ); > flags =3D FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_= stride); > flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_= bits); > - flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env= )); > - flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(e= nv)); > if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) > || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)= ) { > flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); > @@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, > flags =3D FIELD_DP32(flags, TBFLAG_A32, > XSCALE_CPAR, env->cp15.c15_cpar); > } > - > - flags =3D rebuild_hflags_common(env, fp_el, mmu_idx, flags); > } > > /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine -- Alex Benn=C3=A9e