From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cW4Bt-0005SU-Az for qemu-devel@nongnu.org; Tue, 24 Jan 2017 11:43:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cW4Bp-0000fP-Dt for qemu-devel@nongnu.org; Tue, 24 Jan 2017 11:43:29 -0500 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:38665) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cW4Bp-0000ev-6p for qemu-devel@nongnu.org; Tue, 24 Jan 2017 11:43:25 -0500 Received: by mail-wm0-x22c.google.com with SMTP id r144so218326343wme.1 for ; Tue, 24 Jan 2017 08:43:24 -0800 (PST) References: <1484937883-1068-1-git-send-email-peter.maydell@linaro.org> <1484937883-1068-4-git-send-email-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1484937883-1068-4-git-send-email-peter.maydell@linaro.org> Date: Tue, 24 Jan 2017 16:43:22 +0000 Message-ID: <87tw8o9zo5.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 3/6] armv7m: Explicit error for bad vector table List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Liviu Ionescu , Michael Davidsaver , patches@linaro.org Peter Maydell writes: > From: Michael Davidsaver > > Give an explicit error and abort when a load > from the vector table fails. Architecturally this > should HardFault (which will then immediately > fail to load the HardFault vector and go into Lockup). > Since we don't model Lockup, just report this guest > error via cpu_abort(). This is more helpful than the > previous behaviour of reading a zero, which is the > address of the reset stack pointer and not a sensible > location to jump to. Word wrap has gone a little aggressive in the commit message ;-) > > Signed-off-by: Michael Davidsaver > Reviewed-by: Peter Maydell > [PMM: expanded commit message] > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 26 +++++++++++++++++++++++++- > 1 file changed, 25 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index ad23de3..8edb08c 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6014,6 +6014,30 @@ static void arm_log_exception(int idx) > } > } > > +static uint32_t arm_v7m_load_vector(ARMCPU *cpu) > + > +{ > + CPUState *cs = CPU(cpu); > + CPUARMState *env = &cpu->env; > + MemTxResult result; > + hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; > + uint32_t addr; > + > + addr = address_space_ldl(cs->as, vec, > + MEMTXATTRS_UNSPECIFIED, &result); > + if (result != MEMTX_OK) { > + /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, > + * which would then be immediately followed by our failing to load > + * the entry vector for that HardFault, which is a Lockup case. > + * Since we don't model Lockup, we just report this guest error > + * via cpu_abort(). > + */ > + cpu_abort(cs, "Failed to read from exception vector table " > + "entry %08x\n", (unsigned)vec); > + } > + return addr; > +} > + > void arm_v7m_cpu_do_interrupt(CPUState *cs) > { > ARMCPU *cpu = ARM_CPU(cs); > @@ -6095,7 +6119,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > /* Clear IT bits */ > env->condexec_bits = 0; > env->regs[14] = lr; > - addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); > + addr = arm_v7m_load_vector(cpu); > env->regs[15] = addr & 0xfffffffe; > env->thumb = addr & 1; > } Reviewed-by: Alex Bennée -- Alex Bennée