From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: Peter Maydell <peter.maydell@linaro.org>,
patches@linaro.org, Michael Matz <matz@suse.de>,
qemu-devel@nongnu.org,
Claudio Fontana <claudio.fontana@linaro.org>,
Dirk Mueller <dmueller@suse.de>,
Will Newton <will.newton@linaro.org>,
Laurent Desnogues <laurent.desnogues@gmail.com>,
kvmarm@lists.cs.columbia.edu,
Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 3/9] target-arm: A64: add support for ld/st unsigned imm
Date: Tue, 10 Dec 2013 14:09:25 +0000 [thread overview]
Message-ID: <87txeg6bmy.fsf@linaro.org> (raw)
In-Reply-To: <52A62FF0.1020303@twiddle.net>
rth@twiddle.net writes:
> On 12/09/2013 10:12 AM, Peter Maydell wrote:
>> From: Alex Bennée <alex.bennee@linaro.org>
<snip>
>>
>> +static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
>> +{
>> + TCGv_i64 v = new_tmp_a64(s);
>> + if (sf) {
>> + tcg_gen_mov_i64(v, cpu_X[reg]);
>> + } else {
>> + tcg_gen_ext32u_i64(v, cpu_X[reg]);
>> + }
>> + return v;
>> +}
>
> Did you want to use this in for the load/store pair insns too?
Yes. Originally I was doing a load of:
tcg_rn = cpu_reg_sp(...)
tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn...
Before we had a clear API for the CPU reg stuff. Now I tend to just do:
tcg_addr = read_cpu_reg_sp(...)
I'll hoist that into the first patch now I've re-done it.
--
Alex Bennée
QEMU/KVM Hacker for Linaro
next prev parent reply other threads:[~2013-12-10 14:09 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 18:12 [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer Peter Maydell
2013-12-09 18:12 ` [Qemu-devel] [PATCH 1/9] target-arm: A64: add support for stp (store pair) Peter Maydell
2013-12-09 20:17 ` Richard Henderson
2013-12-10 14:05 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 2/9] target-arm: A64: add support for ldp (load pair) Peter Maydell
2013-12-09 20:25 ` Richard Henderson
2013-12-10 13:59 ` Alex Bennée
2013-12-10 16:58 ` Richard Henderson
2013-12-10 17:41 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 3/9] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2013-12-09 21:02 ` Richard Henderson
2013-12-10 14:09 ` Alex Bennée [this message]
2013-12-09 18:12 ` [Qemu-devel] [PATCH 4/9] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2013-12-09 21:09 ` Richard Henderson
2013-12-10 14:16 ` Alex Bennée
2013-12-10 15:59 ` Richard Henderson
2013-12-11 22:01 ` Alex Bennée
2013-12-09 18:12 ` [Qemu-devel] [PATCH 5/9] target-arm: A64: add support for ld/st with index Peter Maydell
2013-12-09 18:12 ` [Qemu-devel] [PATCH 6/9] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2013-12-09 21:36 ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 7/9] target-arm: A64: add support for move wide instructions Peter Maydell
2013-12-09 21:42 ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 8/9] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2013-12-09 21:52 ` Richard Henderson
2013-12-09 18:12 ` [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK Peter Maydell
2013-12-09 21:58 ` Richard Henderson
2013-12-09 22:14 ` Peter Maydell
2013-12-09 18:16 ` [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer Peter Maydell
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