[Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Richard Henderson]

This patch set includes both the remainder series and arm runtime
detection series that I've previouslyt posted separately, as there
are small conflicts between the two series.

Aside from rebasing vs master, the only other change is to fix the
TCG_OPF_NOT_PRESENT problem wrt call that Claudio Fontana spotted.


r~


Richard Henderson (9):
  tcg: Split rem requirement from div requirement
  tcg-arm: Don't implement rem
  tcg-ppc: Don't implement rem
  tcg-ppc64: Don't implement rem
  tcg: Allow non-constant control macros
  tcg: Simplify logic using TCG_OPF_NOT_PRESENT
  tcg-arm: Make use of conditional availability of opcodes for divide
  tcg-arm: Simplify logic in detecting the ARM ISA in use
  tcg-arm: Use AT_PLATFORM to detect the host ISA

 tcg/arm/tcg-target.c   | 96 ++++++++++++++++++++++----------------------------
 tcg/arm/tcg-target.h   | 15 ++++----
 tcg/hppa/tcg-target.h  |  1 +
 tcg/ia64/tcg-target.h  |  2 ++
 tcg/mips/tcg-target.h  |  1 +
 tcg/ppc/tcg-target.c   | 14 --------
 tcg/ppc/tcg-target.h   |  1 +
 tcg/ppc64/tcg-target.c | 26 --------------
 tcg/ppc64/tcg-target.h |  2 ++
 tcg/sparc/tcg-target.h |  2 ++
 tcg/tcg-op.h           | 32 ++++++++++++++---
 tcg/tcg-opc.h          | 36 ++++++++++---------
 tcg/tcg.c              |  4 +--
 tcg/tcg.h              |  6 +++-
 tcg/tci/tcg-target.h   |  2 ++
 15 files changed, 116 insertions(+), 124 deletions(-)

-- 
1.8.1.4

[Qemu-devel] [PATCH v2 1/9] tcg: Split rem requirement from div requirement

[Richard Henderson]

There are several hosts with only a "div" insn.  Remainder is computed
manually from the quotient and inputs.  We can do this generically.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.h   |  2 ++
 tcg/hppa/tcg-target.h  |  1 +
 tcg/ia64/tcg-target.h  |  2 ++
 tcg/mips/tcg-target.h  |  1 +
 tcg/ppc/tcg-target.h   |  1 +
 tcg/ppc64/tcg-target.h |  2 ++
 tcg/sparc/tcg-target.h |  2 ++
 tcg/tcg-op.h           | 32 ++++++++++++++++++++++++++++----
 tcg/tcg-opc.h          |  8 ++++----
 tcg/tcg.h              |  3 +++
 tcg/tci/tcg-target.h   |  2 ++
 11 files changed, 48 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 3be41cc..2c5b4e7 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -76,8 +76,10 @@ typedef enum {
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #else
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #endif
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index ebd53d9..25467bd 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -85,6 +85,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index e3d72ea..f32d519 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -104,7 +104,9 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_andc_i32         1
 #define TCG_TARGET_HAS_andc_i64         1
 #define TCG_TARGET_HAS_bswap16_i32      1
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 6155327..a438950 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -79,6 +79,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_not_i32          1
 #define TCG_TARGET_HAS_nor_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 17a6bb3..01b880e 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -78,6 +78,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index cb77634..7c600f1 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -76,6 +76,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -96,6 +97,7 @@ typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          1
+#define TCG_TARGET_HAS_rem_i64          1
 #define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index b5217be..dab52d7 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -86,6 +86,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32		1
+#define TCG_TARGET_HAS_rem_i32		1
 #define TCG_TARGET_HAS_rot_i32          0
 #define TCG_TARGET_HAS_ext8s_i32        0
 #define TCG_TARGET_HAS_ext16s_i32       0
@@ -109,6 +110,7 @@ typedef enum {
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_div_i64          1
+#define TCG_TARGET_HAS_rem_i64          1
 #define TCG_TARGET_HAS_rot_i64          0
 #define TCG_TARGET_HAS_ext8s_i64        0
 #define TCG_TARGET_HAS_ext16s_i64       0
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 94f6043..364964d 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -731,8 +731,14 @@ static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 
 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
-    if (TCG_TARGET_HAS_div_i32) {
+    if (TCG_TARGET_HAS_rem_i32) {
         tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i32) {
+        TCGv_i32 t0 = tcg_temp_new_i32();
+        tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
+        tcg_gen_mul_i32(t0, t0, arg2);
+        tcg_gen_sub_i32(ret, arg1, t0);
+        tcg_temp_free_i32(t0);
     } else if (TCG_TARGET_HAS_div2_i32) {
         TCGv_i32 t0 = tcg_temp_new_i32();
         tcg_gen_sari_i32(t0, arg1, 31);
@@ -769,8 +775,14 @@ static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 
 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
-    if (TCG_TARGET_HAS_div_i32) {
+    if (TCG_TARGET_HAS_rem_i32) {
         tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i32) {
+        TCGv_i32 t0 = tcg_temp_new_i32();
+        tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
+        tcg_gen_mul_i32(t0, t0, arg2);
+        tcg_gen_sub_i32(ret, arg1, t0);
+        tcg_temp_free_i32(t0);
     } else if (TCG_TARGET_HAS_div2_i32) {
         TCGv_i32 t0 = tcg_temp_new_i32();
         tcg_gen_movi_i32(t0, 0);
@@ -1361,8 +1373,14 @@ static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
-    if (TCG_TARGET_HAS_div_i64) {
+    if (TCG_TARGET_HAS_rem_i64) {
         tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i64) {
+        TCGv_i64 t0 = tcg_temp_new_i64();
+        tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
+        tcg_gen_mul_i64(t0, t0, arg2);
+        tcg_gen_sub_i64(ret, arg1, t0);
+        tcg_temp_free_i64(t0);
     } else if (TCG_TARGET_HAS_div2_i64) {
         TCGv_i64 t0 = tcg_temp_new_i64();
         tcg_gen_sari_i64(t0, arg1, 63);
@@ -1399,8 +1417,14 @@ static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
-    if (TCG_TARGET_HAS_div_i64) {
+    if (TCG_TARGET_HAS_rem_i64) {
         tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
+    } else if (TCG_TARGET_HAS_div_i64) {
+        TCGv_i64 t0 = tcg_temp_new_i64();
+        tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
+        tcg_gen_mul_i64(t0, t0, arg2);
+        tcg_gen_sub_i64(ret, arg1, t0);
+        tcg_temp_free_i64(t0);
     } else if (TCG_TARGET_HAS_div2_i64) {
         TCGv_i64 t0 = tcg_temp_new_i64();
         tcg_gen_movi_i64(t0, 0);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4246e9c..12967fb 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -66,8 +66,8 @@ DEF(sub_i32, 1, 2, 0, 0)
 DEF(mul_i32, 1, 2, 0, 0)
 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
-DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
-DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
+DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
+DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
 DEF(and_i32, 1, 2, 0, 0)
@@ -126,8 +126,8 @@ DEF(sub_i64, 1, 2, 0, IMPL64)
 DEF(mul_i64, 1, 2, 0, IMPL64)
 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
-DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
-DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
+DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
+DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 DEF(and_i64, 1, 2, 0, IMPL64)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index df375cf..28ca1bd 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -60,6 +60,7 @@ typedef uint64_t TCGRegSet;
 #if TCG_TARGET_REG_BITS == 32
 /* Turn some undef macros into false macros.  */
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_div2_i64         0
 #define TCG_TARGET_HAS_rot_i64          0
 #define TCG_TARGET_HAS_ext8s_i64        0
@@ -102,11 +103,13 @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_div2_i32         0
 #elif defined(TCG_TARGET_HAS_div2_i32)
 #define TCG_TARGET_HAS_div_i32          0
+#define TCG_TARGET_HAS_rem_i32          0
 #endif
 #if defined(TCG_TARGET_HAS_div_i64)
 #define TCG_TARGET_HAS_div2_i64         0
 #elif defined(TCG_TARGET_HAS_div2_i64)
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #endif
 
 typedef enum TCGOpcode {
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 0395bbb..9aa1256 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -61,6 +61,7 @@
 #define TCG_TARGET_HAS_bswap32_i32      1
 /* Not more than one of the next two defines must be 1. */
 #define TCG_TARGET_HAS_div_i32          1
+#define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_div2_i32         0
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -85,6 +86,7 @@
 #define TCG_TARGET_HAS_deposit_i64      1
 /* Not more than one of the next two defines must be 1. */
 #define TCG_TARGET_HAS_div_i64          0
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_div2_i64         0
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 2/9] tcg-arm: Don't implement rem

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 14 --------------
 tcg/arm/tcg-target.h |  3 +--
 2 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 6be736b..8321f80 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1926,18 +1926,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_divu_i32:
         tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
         break;
-    case INDEX_op_rem_i32:
-        tcg_out_sdiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]);
-        tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]);
-        tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP,
-                        SHIFT_IMM_LSL(0));
-        break;
-    case INDEX_op_remu_i32:
-        tcg_out_udiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]);
-        tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]);
-        tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP,
-                        SHIFT_IMM_LSL(0));
-        break;
 
     default:
         tcg_abort();
@@ -2043,9 +2031,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
 #if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
 #endif
 
     { -1 },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 2c5b4e7..263ea03 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -76,11 +76,10 @@ typedef enum {
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
 #else
 #define TCG_TARGET_HAS_div_i32          0
-#define TCG_TARGET_HAS_rem_i32          0
 #endif
+#define TCG_TARGET_HAS_rem_i32          0
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
 #define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 3/9] tcg-ppc: Don't implement rem

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc/tcg-target.c | 14 --------------
 tcg/ppc/tcg-target.h |  2 +-
 2 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 29ca934..453ab6b 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1671,18 +1671,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
         tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
         break;
 
-    case INDEX_op_rem_i32:
-        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
-    case INDEX_op_remu_i32:
-        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
     case INDEX_op_mulu2_i32:
         if (args[0] == args[2] || args[0] == args[3]) {
             tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
@@ -1992,8 +1980,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i32, { "r", "r", "ri" } },
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
     { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
     { INDEX_op_sub_i32, { "r", "r", "ri" } },
     { INDEX_op_and_i32, { "r", "r", "ri" } },
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 01b880e..b42d97c 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -78,7 +78,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 4/9] tcg-ppc64: Don't implement rem

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 26 --------------------------
 tcg/ppc64/tcg-target.h |  4 ++--
 2 files changed, 2 insertions(+), 28 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 606b73d..0678de2 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1617,18 +1617,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
         tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
         break;
 
-    case INDEX_op_rem_i32:
-        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
-    case INDEX_op_remu_i32:
-        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-
     case INDEX_op_shl_i32:
         if (const_args[2]) {
             tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
@@ -1786,16 +1774,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
     case INDEX_op_divu_i64:
         tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
         break;
-    case INDEX_op_rem_i64:
-        tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
-    case INDEX_op_remu_i64:
-        tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
-        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
-        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
-        break;
 
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld (s, args, 0);
@@ -2064,8 +2042,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i32, { "r", "r", "rI" } },
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-    { INDEX_op_rem_i32, { "r", "r", "r" } },
-    { INDEX_op_remu_i32, { "r", "r", "r" } },
     { INDEX_op_sub_i32, { "r", "rI", "ri" } },
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
@@ -2108,8 +2084,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_mul_i64, { "r", "r", "rI" } },
     { INDEX_op_div_i64, { "r", "r", "r" } },
     { INDEX_op_divu_i64, { "r", "r", "r" } },
-    { INDEX_op_rem_i64, { "r", "r", "r" } },
-    { INDEX_op_remu_i64, { "r", "r", "r" } },
 
     { INDEX_op_neg_i64, { "r", "r" } },
     { INDEX_op_not_i64, { "r", "r" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 7c600f1..48fc6e2 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -76,7 +76,7 @@ typedef enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32          1
-#define TCG_TARGET_HAS_rem_i32          1
+#define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_ext8s_i32        1
 #define TCG_TARGET_HAS_ext16s_i32       1
@@ -97,7 +97,7 @@ typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 
 #define TCG_TARGET_HAS_div_i64          1
-#define TCG_TARGET_HAS_rem_i64          1
+#define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_ext8s_i64        1
 #define TCG_TARGET_HAS_ext16s_i64       1
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 5/9] tcg: Allow non-constant control macros

[Richard Henderson]

This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
which allows easier support for differing ISA levels for the host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-opc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 12967fb..c94e255 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -40,7 +40,7 @@ DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
 DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 
-#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
+#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
 #if TCG_TARGET_REG_BITS == 32
 # define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
 #else
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 6/9] tcg: Simplify logic using TCG_OPF_NOT_PRESENT

[Richard Henderson]

Expand the definition of "not present" to include "should not be present".
This means we can simplify the logic surrounding the generic tcg opcodes
for which the host backend ought not be providing definitions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-opc.h | 26 +++++++++++++++-----------
 tcg/tcg.c     |  4 +---
 tcg/tcg.h     |  3 ++-
 3 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index c94e255..a8af5b9 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -27,17 +27,21 @@
  */
 
 /* predefined ops */
-DEF(end, 0, 0, 0, 0) /* must be kept first */
-DEF(nop, 0, 0, 0, 0)
-DEF(nop1, 0, 0, 1, 0)
-DEF(nop2, 0, 0, 2, 0)
-DEF(nop3, 0, 0, 3, 0)
-DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
+DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
+DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
+DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
+DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
 
-DEF(discard, 1, 0, 0, 0)
+/* variable number of parameters */
+DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+
+DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
+DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
+
+/* variable number of parameters */
+DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER)
 
-DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
-DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 
 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
@@ -166,9 +170,9 @@ DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 
 /* QEMU specific */
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-DEF(debug_insn_start, 0, 0, 2, 0)
+DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
 #else
-DEF(debug_insn_start, 0, 0, 1, 0)
+DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
 #endif
 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1d8099c..c7e6567 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1160,9 +1160,7 @@ void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
     i = 0;
     for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
         const TCGOpDef *def = &tcg_op_defs[op];
-        if (op < INDEX_op_call
-            || op == INDEX_op_debug_insn_start
-            || (def->flags & TCG_OPF_NOT_PRESENT)) {
+        if (def->flags & TCG_OPF_NOT_PRESENT) {
             /* Wrong entry in op definitions? */
             if (def->used) {
                 fprintf(stderr, "Invalid op definition for %s\n", def->name);
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 28ca1bd..f3f9889 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -596,7 +596,8 @@ enum {
     TCG_OPF_SIDE_EFFECTS = 0x04,
     /* Instruction operands are 64-bits (otherwise 32-bits).  */
     TCG_OPF_64BIT        = 0x08,
-    /* Instruction is optional and not implemented by the host.  */
+    /* Instruction is optional and not implemented by the host, or insn
+       is generic and should not be implemened by the host.  */
     TCG_OPF_NOT_PRESENT  = 0x10,
 };
 
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 7/9] tcg-arm: Make use of conditional availability of opcodes for divide

[Richard Henderson]

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 16 ++++++++++++++--
 tcg/arm/tcg-target.h | 14 ++++++++------
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 8321f80..2c46ceb 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
 #endif
 #undef USE_ARMV7_INSTRUCTIONS
 
+#ifndef use_idiv_instructions
+bool use_idiv_instructions;
+#endif
+#ifdef CONFIG_GETAUXVAL
+# include <sys/auxv.h>
+#endif
+
 #ifndef NDEBUG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
     "%r0",
@@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
     { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
 
-#if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
-#endif
 
     { -1 },
 };
 
 static void tcg_target_init(TCGContext *s)
 {
+#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+    {
+        unsigned long hwcap = getauxval(AT_HWCAP);
+        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
+    }
+#endif
+
     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
                      (1 << TCG_REG_R0) |
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 263ea03..5cd9d6a 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -49,6 +49,13 @@ typedef enum {
 
 #define TCG_TARGET_NB_REGS 16
 
+#ifdef __ARM_ARCH_EXT_IDIV__
+#define use_idiv_instructions  1
+#else
+extern bool use_idiv_instructions;
+#endif
+
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
@@ -73,12 +80,7 @@ typedef enum {
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_muls2_i32        1
-
-#ifdef __ARM_ARCH_EXT_IDIV__
-#define TCG_TARGET_HAS_div_i32          1
-#else
-#define TCG_TARGET_HAS_div_i32          0
-#endif
+#define TCG_TARGET_HAS_div_i32          use_idiv_instructions
 #define TCG_TARGET_HAS_rem_i32          0
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 8/9] tcg-arm: Simplify logic in detecting the ARM ISA in use

[Richard Henderson]

GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which
will make us nicely forward compatible with ARMv8 AArch32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 62 +++++++++++++++++-----------------------------------
 1 file changed, 20 insertions(+), 42 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 2c46ceb..763b173 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -22,50 +22,28 @@
  * THE SOFTWARE.
  */
 
-#if defined(__ARM_ARCH_7__) ||  \
-    defined(__ARM_ARCH_7A__) || \
-    defined(__ARM_ARCH_7EM__) || \
-    defined(__ARM_ARCH_7M__) || \
-    defined(__ARM_ARCH_7R__)
-#define USE_ARMV7_INSTRUCTIONS
+/* The __ARM_ARCH define is provided by gcc 4.8.  Construct it otherwise.  */
+#ifndef __ARM_ARCH
+# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
+     || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
+     || defined(__ARM_ARCH_7EM__)
+#  define __ARM_ARCH 7
+# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
+       || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
+       || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
+#  define __ARM_ARCH 6
+# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
+       || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
+       || defined(__ARM_ARCH_5TEJ__)
+#  define __ARM_ARCH 5
+# else
+#  define __ARM_ARCH 4
+# endif
 #endif
 
-#if defined(USE_ARMV7_INSTRUCTIONS) || \
-    defined(__ARM_ARCH_6J__) || \
-    defined(__ARM_ARCH_6K__) || \
-    defined(__ARM_ARCH_6T2__) || \
-    defined(__ARM_ARCH_6Z__) || \
-    defined(__ARM_ARCH_6ZK__)
-#define USE_ARMV6_INSTRUCTIONS
-#endif
-
-#if defined(USE_ARMV6_INSTRUCTIONS) || \
-    defined(__ARM_ARCH_5T__) || \
-    defined(__ARM_ARCH_5TE__) || \
-    defined(__ARM_ARCH_5TEJ__)
-#define USE_ARMV5_INSTRUCTIONS
-#endif
-
-#ifdef USE_ARMV5_INSTRUCTIONS
-static const int use_armv5_instructions = 1;
-#else
-static const int use_armv5_instructions = 0;
-#endif
-#undef USE_ARMV5_INSTRUCTIONS
-
-#ifdef USE_ARMV6_INSTRUCTIONS
-static const int use_armv6_instructions = 1;
-#else
-static const int use_armv6_instructions = 0;
-#endif
-#undef USE_ARMV6_INSTRUCTIONS
-
-#ifdef USE_ARMV7_INSTRUCTIONS
-static const int use_armv7_instructions = 1;
-#else
-static const int use_armv7_instructions = 0;
-#endif
-#undef USE_ARMV7_INSTRUCTIONS
+#define use_armv5_instructions  (__ARM_ARCH >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
-- 
1.8.1.4

[Qemu-devel] [PATCH v2 9/9] tcg-arm: Use AT_PLATFORM to detect the host ISA

[Richard Henderson]

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator.  The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are
optimized away.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 763b173..a46d2e0 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -41,9 +41,11 @@
 # endif
 #endif
 
-#define use_armv5_instructions  (__ARM_ARCH >= 5)
-#define use_armv6_instructions  (__ARM_ARCH >= 6)
-#define use_armv7_instructions  (__ARM_ARCH >= 7)
+static int arm_arch = __ARM_ARCH;
+
+#define use_armv5_instructions  (__ARM_ARCH >= 5 || arm_arch >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
@@ -2022,12 +2024,22 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
 static void tcg_target_init(TCGContext *s)
 {
-#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+#if defined(CONFIG_GETAUXVAL)
+    /* Only probe for the platform and capabilities if we havn't already
+       determined maximum values at compile time.  */
+# if !defined(use_idiv_instructions)
     {
         unsigned long hwcap = getauxval(AT_HWCAP);
         use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
     }
-#endif
+# endif
+    if (__ARM_ARCH < 7) {
+        const char *pl = (const char *)getauxval(AT_PLATFORM);
+        if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
+            arm_arch = pl[1] - '0';
+        }
+    }
+#endif /* GETAUXVAL */
 
     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Richard Henderson]

Ping.

On 06/26/2013 01:52 PM, Richard Henderson wrote:
> This patch set includes both the remainder series and arm runtime
> detection series that I've previouslyt posted separately, as there
> are small conflicts between the two series.
> 
> Aside from rebasing vs master, the only other change is to fix the
> TCG_OPF_NOT_PRESENT problem wrt call that Claudio Fontana spotted.
> 
> 
> r~
> 
> 
> Richard Henderson (9):
>   tcg: Split rem requirement from div requirement
>   tcg-arm: Don't implement rem
>   tcg-ppc: Don't implement rem
>   tcg-ppc64: Don't implement rem
>   tcg: Allow non-constant control macros
>   tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>   tcg-arm: Make use of conditional availability of opcodes for divide
>   tcg-arm: Simplify logic in detecting the ARM ISA in use
>   tcg-arm: Use AT_PLATFORM to detect the host ISA
> 
>  tcg/arm/tcg-target.c   | 96 ++++++++++++++++++++++----------------------------
>  tcg/arm/tcg-target.h   | 15 ++++----
>  tcg/hppa/tcg-target.h  |  1 +
>  tcg/ia64/tcg-target.h  |  2 ++
>  tcg/mips/tcg-target.h  |  1 +
>  tcg/ppc/tcg-target.c   | 14 --------
>  tcg/ppc/tcg-target.h   |  1 +
>  tcg/ppc64/tcg-target.c | 26 --------------
>  tcg/ppc64/tcg-target.h |  2 ++
>  tcg/sparc/tcg-target.h |  2 ++
>  tcg/tcg-op.h           | 32 ++++++++++++++---
>  tcg/tcg-opc.h          | 36 ++++++++++---------
>  tcg/tcg.c              |  4 +--
>  tcg/tcg.h              |  6 +++-
>  tcg/tci/tcg-target.h   |  2 ++
>  15 files changed, 116 insertions(+), 124 deletions(-)
> 

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Anthony Liguori]

Richard Henderson <rth@twiddle.net> writes:

> Ping.

Peter, could you take a look and bring in through the arm tree?

Regards,

Anthony Liguori

>
> On 06/26/2013 01:52 PM, Richard Henderson wrote:
>> This patch set includes both the remainder series and arm runtime
>> detection series that I've previouslyt posted separately, as there
>> are small conflicts between the two series.
>> 
>> Aside from rebasing vs master, the only other change is to fix the
>> TCG_OPF_NOT_PRESENT problem wrt call that Claudio Fontana spotted.
>> 
>> 
>> r~
>> 
>> 
>> Richard Henderson (9):
>>   tcg: Split rem requirement from div requirement
>>   tcg-arm: Don't implement rem
>>   tcg-ppc: Don't implement rem
>>   tcg-ppc64: Don't implement rem
>>   tcg: Allow non-constant control macros
>>   tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>>   tcg-arm: Make use of conditional availability of opcodes for divide
>>   tcg-arm: Simplify logic in detecting the ARM ISA in use
>>   tcg-arm: Use AT_PLATFORM to detect the host ISA
>> 
>>  tcg/arm/tcg-target.c   | 96 ++++++++++++++++++++++----------------------------
>>  tcg/arm/tcg-target.h   | 15 ++++----
>>  tcg/hppa/tcg-target.h  |  1 +
>>  tcg/ia64/tcg-target.h  |  2 ++
>>  tcg/mips/tcg-target.h  |  1 +
>>  tcg/ppc/tcg-target.c   | 14 --------
>>  tcg/ppc/tcg-target.h   |  1 +
>>  tcg/ppc64/tcg-target.c | 26 --------------
>>  tcg/ppc64/tcg-target.h |  2 ++
>>  tcg/sparc/tcg-target.h |  2 ++
>>  tcg/tcg-op.h           | 32 ++++++++++++++---
>>  tcg/tcg-opc.h          | 36 ++++++++++---------
>>  tcg/tcg.c              |  4 +--
>>  tcg/tcg.h              |  6 +++-
>>  tcg/tci/tcg-target.h   |  2 ++
>>  15 files changed, 116 insertions(+), 124 deletions(-)
>> 

Re: [Qemu-devel] [PATCH v2 3/9] tcg-ppc: Don't implement rem

[Andreas Färber]

Am 26.06.2013 22:52, schrieb Richard Henderson:
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Andreas

> ---
>  tcg/ppc/tcg-target.c | 14 --------------
>  tcg/ppc/tcg-target.h |  2 +-
>  2 files changed, 1 insertion(+), 15 deletions(-)
> 
> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
> index 29ca934..453ab6b 100644
> --- a/tcg/ppc/tcg-target.c
> +++ b/tcg/ppc/tcg-target.c
> @@ -1671,18 +1671,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
>          tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
>          break;
>  
> -    case INDEX_op_rem_i32:
> -        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -
> -    case INDEX_op_remu_i32:
> -        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -
>      case INDEX_op_mulu2_i32:
>          if (args[0] == args[2] || args[0] == args[3]) {
>              tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
> @@ -1992,8 +1980,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_mul_i32, { "r", "r", "ri" } },
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
> -    { INDEX_op_rem_i32, { "r", "r", "r" } },
> -    { INDEX_op_remu_i32, { "r", "r", "r" } },
>      { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
>      { INDEX_op_sub_i32, { "r", "r", "ri" } },
>      { INDEX_op_and_i32, { "r", "r", "ri" } },
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 01b880e..b42d97c 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -78,7 +78,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
> -#define TCG_TARGET_HAS_rem_i32          1
> +#define TCG_TARGET_HAS_rem_i32          0
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> 


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 4/9] tcg-ppc64: Don't implement rem

[Andreas Färber]

Am 26.06.2013 22:52, schrieb Richard Henderson:
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Andreas

> ---
>  tcg/ppc64/tcg-target.c | 26 --------------------------
>  tcg/ppc64/tcg-target.h |  4 ++--
>  2 files changed, 2 insertions(+), 28 deletions(-)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 606b73d..0678de2 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1617,18 +1617,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>          tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
>          break;
>  
> -    case INDEX_op_rem_i32:
> -        tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -
> -    case INDEX_op_remu_i32:
> -        tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -
>      case INDEX_op_shl_i32:
>          if (const_args[2]) {
>              tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
> @@ -1786,16 +1774,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>      case INDEX_op_divu_i64:
>          tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
>          break;
> -    case INDEX_op_rem_i64:
> -        tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
> -    case INDEX_op_remu_i64:
> -        tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
> -        tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
> -        tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
> -        break;
>  
>      case INDEX_op_qemu_ld8u:
>          tcg_out_qemu_ld (s, args, 0);
> @@ -2064,8 +2042,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_mul_i32, { "r", "r", "rI" } },
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
> -    { INDEX_op_rem_i32, { "r", "r", "r" } },
> -    { INDEX_op_remu_i32, { "r", "r", "r" } },
>      { INDEX_op_sub_i32, { "r", "rI", "ri" } },
>      { INDEX_op_and_i32, { "r", "r", "ri" } },
>      { INDEX_op_or_i32, { "r", "r", "ri" } },
> @@ -2108,8 +2084,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_mul_i64, { "r", "r", "rI" } },
>      { INDEX_op_div_i64, { "r", "r", "r" } },
>      { INDEX_op_divu_i64, { "r", "r", "r" } },
> -    { INDEX_op_rem_i64, { "r", "r", "r" } },
> -    { INDEX_op_remu_i64, { "r", "r", "r" } },
>  
>      { INDEX_op_neg_i64, { "r", "r" } },
>      { INDEX_op_not_i64, { "r", "r" } },
> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
> index 7c600f1..48fc6e2 100644
> --- a/tcg/ppc64/tcg-target.h
> +++ b/tcg/ppc64/tcg-target.h
> @@ -76,7 +76,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
> -#define TCG_TARGET_HAS_rem_i32          1
> +#define TCG_TARGET_HAS_rem_i32          0
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> @@ -97,7 +97,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_muls2_i32        0
>  
>  #define TCG_TARGET_HAS_div_i64          1
> -#define TCG_TARGET_HAS_rem_i64          1
> +#define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_rot_i64          1
>  #define TCG_TARGET_HAS_ext8s_i64        1
>  #define TCG_TARGET_HAS_ext16s_i64       1
> 


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Andreas Färber]

Am 02.07.2013 21:17, schrieb Anthony Liguori:
> Richard Henderson <rth@twiddle.net> writes:
> 
>> Ping.
> 
> Peter, could you take a look and bring in through the arm tree?

The ppc bits look pretty obvious and the rem concept fine to me.
Didn't look too close at the arm parts.

Andreas

> 
> Regards,
> 
> Anthony Liguori
> 
>>
>> On 06/26/2013 01:52 PM, Richard Henderson wrote:
>>> This patch set includes both the remainder series and arm runtime
>>> detection series that I've previouslyt posted separately, as there
>>> are small conflicts between the two series.
>>>
>>> Aside from rebasing vs master, the only other change is to fix the
>>> TCG_OPF_NOT_PRESENT problem wrt call that Claudio Fontana spotted.
>>>
>>>
>>> r~
>>>
>>>
>>> Richard Henderson (9):
>>>   tcg: Split rem requirement from div requirement
>>>   tcg-arm: Don't implement rem
>>>   tcg-ppc: Don't implement rem
>>>   tcg-ppc64: Don't implement rem
>>>   tcg: Allow non-constant control macros
>>>   tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>>>   tcg-arm: Make use of conditional availability of opcodes for divide
>>>   tcg-arm: Simplify logic in detecting the ARM ISA in use
>>>   tcg-arm: Use AT_PLATFORM to detect the host ISA
>>>
>>>  tcg/arm/tcg-target.c   | 96 ++++++++++++++++++++++----------------------------
>>>  tcg/arm/tcg-target.h   | 15 ++++----
>>>  tcg/hppa/tcg-target.h  |  1 +
>>>  tcg/ia64/tcg-target.h  |  2 ++
>>>  tcg/mips/tcg-target.h  |  1 +
>>>  tcg/ppc/tcg-target.c   | 14 --------
>>>  tcg/ppc/tcg-target.h   |  1 +
>>>  tcg/ppc64/tcg-target.c | 26 --------------
>>>  tcg/ppc64/tcg-target.h |  2 ++
>>>  tcg/sparc/tcg-target.h |  2 ++
>>>  tcg/tcg-op.h           | 32 ++++++++++++++---
>>>  tcg/tcg-opc.h          | 36 ++++++++++---------
>>>  tcg/tcg.c              |  4 +--
>>>  tcg/tcg.h              |  6 +++-
>>>  tcg/tci/tcg-target.h   |  2 ++
>>>  15 files changed, 116 insertions(+), 124 deletions(-)
>>>
> 
> 


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Peter Maydell]

On 2 July 2013 20:17, Anthony Liguori <aliguori@us.ibm.com> wrote:
> Richard Henderson <rth@twiddle.net> writes:
>
>> Ping.
>
> Peter, could you take a look and bring in through the arm tree?

I can test it and put together a pullrequest, sure, though
tcg/arm isn't really covered by either arm-devs or target-arm.

-- PMM

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Anthony Liguori]

Peter Maydell <peter.maydell@linaro.org> writes:

> On 2 July 2013 20:17, Anthony Liguori <aliguori@us.ibm.com> wrote:
>> Richard Henderson <rth@twiddle.net> writes:
>>
>>> Ping.
>>
>> Peter, could you take a look and bring in through the arm tree?
>
> I can test it and put together a pullrequest, sure, though
> tcg/arm isn't really covered by either arm-devs or target-arm.

Ah, I had assumed you also maintained ARM TCG host support.

MAINTAINERS is silent on TCG host support :-/

Regards,

Anthony Liguori

>
> -- PMM

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Andreas Färber]

Am 02.07.2013 22:25, schrieb Anthony Liguori:
> Peter Maydell <peter.maydell@linaro.org> writes:
>> On 2 July 2013 20:17, Anthony Liguori <aliguori@us.ibm.com> wrote:
>>> Peter, could you take a look and bring in through the arm tree?
>>
>> I can test it and put together a pullrequest, sure, though
>> tcg/arm isn't really covered by either arm-devs or target-arm.
> 
> Ah, I had assumed you also maintained ARM TCG host support.
> 
> MAINTAINERS is silent on TCG host support :-/

Actually it isn't:

Tiny Code Generator (TCG)
-------------------------
Common code
M: qemu-devel@nongnu.org
S: Maintained
F: tcg/

[...]

ARM target
M: Andrzej Zaborowski <balrogg@gmail.com>
S: Maintained
F: tcg/arm/

but that doesn't quite reflect reality anymore. ;)

Richard, don't you want to put yourself there for the common code?
You're the most active on core TCG these days and you could just send a
PULL when there's no more comments after a ping.

Regards,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection

[Peter Maydell]

On 2 July 2013 21:25, Anthony Liguori <aliguori@us.ibm.com> wrote:
> Peter Maydell <peter.maydell@linaro.org> writes:
>> On 2 July 2013 20:17, Anthony Liguori <aliguori@us.ibm.com> wrote:
>>> Richard Henderson <rth@twiddle.net> writes:
>>>
>>>> Ping.
>>>
>>> Peter, could you take a look and bring in through the arm tree?
>>
>> I can test it and put together a pullrequest, sure, though
>> tcg/arm isn't really covered by either arm-devs or target-arm.
>
> Ah, I had assumed you also maintained ARM TCG host support.

I care if it's broken, but I can't say I test it regularly, and
I wouldn't go so far as to call myself actually a maintainer
(partly because I feel like if I pick up any more random subtrees
I won't be doing anything but reviewing patches and putting
together pull requests ;-).

-- PMM

Re: [Qemu-devel] [PATCH v2 1/9] tcg: Split rem requirement from div requirement

[Claudio Fontana]

Hi Richard,

On 26.06.2013 22:52, Richard Henderson wrote:
> There are several hosts with only a "div" insn.  Remainder is computed
> manually from the quotient and inputs.  We can do this generically.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/arm/tcg-target.h   |  2 ++
>  tcg/hppa/tcg-target.h  |  1 +
>  tcg/ia64/tcg-target.h  |  2 ++
>  tcg/mips/tcg-target.h  |  1 +
>  tcg/ppc/tcg-target.h   |  1 +
>  tcg/ppc64/tcg-target.h |  2 ++
>  tcg/sparc/tcg-target.h |  2 ++
>  tcg/tcg-op.h           | 32 ++++++++++++++++++++++++++++----
>  tcg/tcg-opc.h          |  8 ++++----
>  tcg/tcg.h              |  3 +++
>  tcg/tci/tcg-target.h   |  2 ++
>  11 files changed, 48 insertions(+), 8 deletions(-)

The list of TCG targets updated is incomplete: at least for aarch64, the patchset breaks compilation because of missing definitions for TCG_TARGET_HAS_rem_i32 and TCG_TARGET_HAS_rem_i64.

Just adding a 
#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_rem_i64 0

for the missing TCG targets should do the trick and keep things working.

Ciao,

Claudio

> 
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 3be41cc..2c5b4e7 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -76,8 +76,10 @@ typedef enum {
>  
>  #ifdef __ARM_ARCH_EXT_IDIV__
>  #define TCG_TARGET_HAS_div_i32          1
> +#define TCG_TARGET_HAS_rem_i32          1
>  #else
>  #define TCG_TARGET_HAS_div_i32          0
> +#define TCG_TARGET_HAS_rem_i32          0
>  #endif
>  
>  extern bool tcg_target_deposit_valid(int ofs, int len);
> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
> index ebd53d9..25467bd 100644
> --- a/tcg/hppa/tcg-target.h
> +++ b/tcg/hppa/tcg-target.h
> @@ -85,6 +85,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          0
> +#define TCG_TARGET_HAS_rem_i32          0
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
> index e3d72ea..f32d519 100644
> --- a/tcg/ia64/tcg-target.h
> +++ b/tcg/ia64/tcg-target.h
> @@ -104,7 +104,9 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          0
> +#define TCG_TARGET_HAS_rem_i32          0
>  #define TCG_TARGET_HAS_div_i64          0
> +#define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_andc_i32         1
>  #define TCG_TARGET_HAS_andc_i64         1
>  #define TCG_TARGET_HAS_bswap16_i32      1
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index 6155327..a438950 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -79,6 +79,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
> +#define TCG_TARGET_HAS_rem_i32          1
>  #define TCG_TARGET_HAS_not_i32          1
>  #define TCG_TARGET_HAS_nor_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 17a6bb3..01b880e 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -78,6 +78,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
> +#define TCG_TARGET_HAS_rem_i32          1
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
> index cb77634..7c600f1 100644
> --- a/tcg/ppc64/tcg-target.h
> +++ b/tcg/ppc64/tcg-target.h
> @@ -76,6 +76,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32          1
> +#define TCG_TARGET_HAS_rem_i32          1
>  #define TCG_TARGET_HAS_rot_i32          1
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> @@ -96,6 +97,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_muls2_i32        0
>  
>  #define TCG_TARGET_HAS_div_i64          1
> +#define TCG_TARGET_HAS_rem_i64          1
>  #define TCG_TARGET_HAS_rot_i64          1
>  #define TCG_TARGET_HAS_ext8s_i64        1
>  #define TCG_TARGET_HAS_ext16s_i64       1
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index b5217be..dab52d7 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -86,6 +86,7 @@ typedef enum {
>  
>  /* optional instructions */
>  #define TCG_TARGET_HAS_div_i32		1
> +#define TCG_TARGET_HAS_rem_i32		1
>  #define TCG_TARGET_HAS_rot_i32          0
>  #define TCG_TARGET_HAS_ext8s_i32        0
>  #define TCG_TARGET_HAS_ext16s_i32       0
> @@ -109,6 +110,7 @@ typedef enum {
>  
>  #if TCG_TARGET_REG_BITS == 64
>  #define TCG_TARGET_HAS_div_i64          1
> +#define TCG_TARGET_HAS_rem_i64          1
>  #define TCG_TARGET_HAS_rot_i64          0
>  #define TCG_TARGET_HAS_ext8s_i64        0
>  #define TCG_TARGET_HAS_ext16s_i64       0
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 94f6043..364964d 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -731,8 +731,14 @@ static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  
>  static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  {
> -    if (TCG_TARGET_HAS_div_i32) {
> +    if (TCG_TARGET_HAS_rem_i32) {
>          tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
> +    } else if (TCG_TARGET_HAS_div_i32) {
> +        TCGv_i32 t0 = tcg_temp_new_i32();
> +        tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
> +        tcg_gen_mul_i32(t0, t0, arg2);
> +        tcg_gen_sub_i32(ret, arg1, t0);
> +        tcg_temp_free_i32(t0);
>      } else if (TCG_TARGET_HAS_div2_i32) {
>          TCGv_i32 t0 = tcg_temp_new_i32();
>          tcg_gen_sari_i32(t0, arg1, 31);
> @@ -769,8 +775,14 @@ static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  
>  static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  {
> -    if (TCG_TARGET_HAS_div_i32) {
> +    if (TCG_TARGET_HAS_rem_i32) {
>          tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
> +    } else if (TCG_TARGET_HAS_div_i32) {
> +        TCGv_i32 t0 = tcg_temp_new_i32();
> +        tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
> +        tcg_gen_mul_i32(t0, t0, arg2);
> +        tcg_gen_sub_i32(ret, arg1, t0);
> +        tcg_temp_free_i32(t0);
>      } else if (TCG_TARGET_HAS_div2_i32) {
>          TCGv_i32 t0 = tcg_temp_new_i32();
>          tcg_gen_movi_i32(t0, 0);
> @@ -1361,8 +1373,14 @@ static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  
>  static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  {
> -    if (TCG_TARGET_HAS_div_i64) {
> +    if (TCG_TARGET_HAS_rem_i64) {
>          tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
> +    } else if (TCG_TARGET_HAS_div_i64) {
> +        TCGv_i64 t0 = tcg_temp_new_i64();
> +        tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
> +        tcg_gen_mul_i64(t0, t0, arg2);
> +        tcg_gen_sub_i64(ret, arg1, t0);
> +        tcg_temp_free_i64(t0);
>      } else if (TCG_TARGET_HAS_div2_i64) {
>          TCGv_i64 t0 = tcg_temp_new_i64();
>          tcg_gen_sari_i64(t0, arg1, 63);
> @@ -1399,8 +1417,14 @@ static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  
>  static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  {
> -    if (TCG_TARGET_HAS_div_i64) {
> +    if (TCG_TARGET_HAS_rem_i64) {
>          tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
> +    } else if (TCG_TARGET_HAS_div_i64) {
> +        TCGv_i64 t0 = tcg_temp_new_i64();
> +        tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
> +        tcg_gen_mul_i64(t0, t0, arg2);
> +        tcg_gen_sub_i64(ret, arg1, t0);
> +        tcg_temp_free_i64(t0);
>      } else if (TCG_TARGET_HAS_div2_i64) {
>          TCGv_i64 t0 = tcg_temp_new_i64();
>          tcg_gen_movi_i64(t0, 0);
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 4246e9c..12967fb 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -66,8 +66,8 @@ DEF(sub_i32, 1, 2, 0, 0)
>  DEF(mul_i32, 1, 2, 0, 0)
>  DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
>  DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
> -DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
> -DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
> +DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
> +DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
>  DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
>  DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
>  DEF(and_i32, 1, 2, 0, 0)
> @@ -126,8 +126,8 @@ DEF(sub_i64, 1, 2, 0, IMPL64)
>  DEF(mul_i64, 1, 2, 0, IMPL64)
>  DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
>  DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
> -DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
> -DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
> +DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
> +DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
>  DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
>  DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
>  DEF(and_i64, 1, 2, 0, IMPL64)
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index df375cf..28ca1bd 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -60,6 +60,7 @@ typedef uint64_t TCGRegSet;
>  #if TCG_TARGET_REG_BITS == 32
>  /* Turn some undef macros into false macros.  */
>  #define TCG_TARGET_HAS_div_i64          0
> +#define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_div2_i64         0
>  #define TCG_TARGET_HAS_rot_i64          0
>  #define TCG_TARGET_HAS_ext8s_i64        0
> @@ -102,11 +103,13 @@ typedef uint64_t TCGRegSet;
>  #define TCG_TARGET_HAS_div2_i32         0
>  #elif defined(TCG_TARGET_HAS_div2_i32)
>  #define TCG_TARGET_HAS_div_i32          0
> +#define TCG_TARGET_HAS_rem_i32          0
>  #endif
>  #if defined(TCG_TARGET_HAS_div_i64)
>  #define TCG_TARGET_HAS_div2_i64         0
>  #elif defined(TCG_TARGET_HAS_div2_i64)
>  #define TCG_TARGET_HAS_div_i64          0
> +#define TCG_TARGET_HAS_rem_i64          0
>  #endif
>  
>  typedef enum TCGOpcode {
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index 0395bbb..9aa1256 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -61,6 +61,7 @@
>  #define TCG_TARGET_HAS_bswap32_i32      1
>  /* Not more than one of the next two defines must be 1. */
>  #define TCG_TARGET_HAS_div_i32          1
> +#define TCG_TARGET_HAS_rem_i32          1
>  #define TCG_TARGET_HAS_div2_i32         0
>  #define TCG_TARGET_HAS_ext8s_i32        1
>  #define TCG_TARGET_HAS_ext16s_i32       1
> @@ -85,6 +86,7 @@
>  #define TCG_TARGET_HAS_deposit_i64      1
>  /* Not more than one of the next two defines must be 1. */
>  #define TCG_TARGET_HAS_div_i64          0
> +#define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_div2_i64         0
>  #define TCG_TARGET_HAS_ext8s_i64        1
>  #define TCG_TARGET_HAS_ext16s_i64       1
> 


-- 
Claudio Fontana
Server OS Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München

office: +49 89 158834 4135
mobile: +49 15253060158

Re: [Qemu-devel] [PATCH v2 1/9] tcg: Split rem requirement from div requirement

[Richard Henderson]

On 07/03/2013 02:07 AM, Claudio Fontana wrote:
> The list of TCG targets updated is incomplete: at least for aarch64, the
> patchset breaks compilation because of missing definitions for
> TCG_TARGET_HAS_rem_i32 and TCG_TARGET_HAS_rem_i64.

Oops.  Sloppy merging, that, failing to add aarch64.  Fixed for next round.


r~