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Fri, 15 Mar 2024 05:25:49 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 2FB025F8A0; Fri, 15 Mar 2024 12:25:49 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: =?utf-8?Q?J=C3=B8rgen?= Hansen Cc: "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "richard.henderson@linaro.org" , Jonathan Cameron , "linux-cxl@vger.kernel.org" Subject: Re: Another CXL/MMIO tcg tlb corner case In-Reply-To: <33748BB7-E617-4661-BDE3-5D29780FC9FF@wdc.com> (=?utf-8?Q?=22?= =?utf-8?Q?J=C3=B8rgen?= Hansen"'s message of "Fri, 15 Mar 2024 09:36:16 +0000") References: <33748BB7-E617-4661-BDE3-5D29780FC9FF@wdc.com> User-Agent: mu4e 1.12.1; emacs 29.2 Date: Fri, 15 Mar 2024 12:25:49 +0000 Message-ID: <87v85n3cmq.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org J=C3=B8rgen Hansen writes: > Hi, > > While doing some testing using numactl-based interleaving of application = memory > across regular memory and CXL-based memory using QEMU with tcg, I ran int= o an > issue similar to what we saw a while back - link to old issue: > https://lore.kernel.org/qemu-devel/CAFEAcA_a_AyQ=3DEpz3_+CheAT8Crsk9mOu89= 4wbNW_FywamkZiw@mail.gmail.com/#t. > > When running: > > numactl --interleave 0,1 ./cachebench =E2=80=A6 > > I hit the following: > > numactl --interleave 0,1 ./cachebench --json_test_config ../test_configs/= hit_ratio/graph_cache_follower_assocs/config.json > qemu: fatal: cpu_io_recompile: could not find TB for pc=3D0x7fffc3926dd4 Ok so this will be because we (by design) don't cache TB's for MMIO regions. But as you say: > > Looking at the tb being executed, it looks like it is a single instructio= n tb, > so with my _very_ limited understanding of tcg, it shouldn=E2=80=99t be n= ecessary to > do the IO recompile: > > (gdb) up 13 > > #13 0x0000555555ca13ac in cpu_loop_exec_tb (tb_exit=3D0x7ffff49ff6d8, las= t_tb=3D, pc=3D, tb=3D0x7fffc3926cc0 , cpu=3D0x5555578c19c0) at ../accel/tcg/cpu-exec.c:904 > 904 tb =3D cpu_tb_exec(cpu, tb, tb_exit); > (gdb) print *tb > $1 =3D {pc =3D 0, cs_base =3D 0, flags =3D 415285939, cflags =3D 42783211= 52, size =3D 7, icount =3D 1, tc =3D {ptr =3D 0x7fffc3926d80 , size =3D 176}, page_next =3D {0, 0}, page_addr =3D {18446744= 073709551615, > 18446744073709551615}, jmp_lock =3D {value =3D 0}, jmp_reset_offset = =3D > {65535, 65535}, jmp_insn_offset =3D {65535, 65535}, jmp_target_addr =3D > {0, 0}, jmp_list_head =3D 140736474540928, jmp_list_next =3D {0, 0}, > jmp_dest =3D {0, 0}} with an icount of 1 we by definition can do io. This is done in the translator_loop: /* * Disassemble one instruction. The translate_insn hook should * update db->pc_next and db->is_jmp to indicate what should be * done next -- either exiting this loop or locate the start of * the next instruction. */ if (db->num_insns =3D=3D db->max_insns) { /* Accept I/O on the last instruction. */ set_can_do_io(db, true); } and we see later on: tb->icount =3D db->num_insns; So I guess we must have gone into the translator loop expecting to translate more? (side note having int8_t type for the saved bool value seems weird). Could you confirm by doing something like: if (tb->icount =3D=3D 1 && db->max_insns > 1) { fprintf(stderr, "ended up doing one insn (%d, %d)", db->max_insns, db-= >saved_can_do_io); } after we set tb->icount? > If the application is run entirely out of MMIO memory, things work fine (= the > previous patches related to this is in Jonathans branch), so one thought = is that > it is related to having the code on a mix of regular and CXL memory. Sinc= e we > previously had issues with code crossing page boundaries where only the s= econd > page is MMIO, I tried out the following change to the fix introduced for = that > issue thinking that reverting to the slow path in the middle of the trans= lation > might not correctly update can_do_io: > > diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c > index 38c34009a5..db6ea360e0 100644 > --- a/accel/tcg/translator.c > +++ b/accel/tcg/translator.c > @@ -258,6 +258,7 @@ static void *translator_access(CPUArchState *env, Dis= asContextBase *db, > if (unlikely(new_page1 =3D=3D -1)) { > tb_unlock_pages(tb); > tb_set_page_addr0(tb, -1); > + set_can_do_io(db, true); > return NULL; > } > > With that change, things work fine. Not saying that this is a valid fix f= or the > issue, but just trying to provide as much information as possible :) I can see why this works, my worry is if we address all the early exit cases here. > > Thanks, > Jorgen --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro