From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org,
qemu-arm@nongnu.org
Subject: Re: [PATCH v6 02/20] target/arm: Split out rebuild_hflags_a64
Date: Mon, 14 Oct 2019 16:43:40 +0100 [thread overview]
Message-ID: <87v9srmixf.fsf@linaro.org> (raw)
In-Reply-To: <20191011155546.14342-3-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> Create a function to compute the values of the TBFLAG_A64 bits
> that will be cached. For now, the env->hflags variable is not
> used, and the results are fed back to cpu_get_tb_cpu_state.
>
> Note that not all BTI related flags are cached, so we have to
> test the BTI feature twice -- once for those bits moved out to
> rebuild_hflags_a64 and once for those bits that remain in
> cpu_get_tb_cpu_state.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/helper.c | 131 +++++++++++++++++++++++---------------------
> 1 file changed, 69 insertions(+), 62 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8829d91ae1..69da04786e 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -11070,6 +11070,71 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
> return flags;
> }
>
> +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
> + ARMMMUIdx mmu_idx)
> +{
> + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
> + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
> + uint32_t flags = 0;
> + uint64_t sctlr;
> + int tbii, tbid;
> +
> + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
> +
> + /* FIXME: ARMv8.1-VHE S2 translation regime. */
> + if (regime_el(env, stage1) < 2) {
> + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
> + tbid = (p1.tbi << 1) | p0.tbi;
> + tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
> + } else {
> + tbid = p0.tbi;
> + tbii = tbid & !p0.tbid;
> + }
> +
> + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
> + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
> +
> + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
> + int sve_el = sve_exception_el(env, el);
> + uint32_t zcr_len;
> +
> + /*
> + * If SVE is disabled, but FP is enabled,
> + * then the effective len is 0.
> + */
> + if (sve_el != 0 && fp_el == 0) {
> + zcr_len = 0;
> + } else {
> + zcr_len = sve_zcr_len_for_el(env, el);
> + }
> + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
> + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
> + }
> +
> + sctlr = arm_sctlr(env, el);
> +
> + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
> + /*
> + * In order to save space in flags, we record only whether
> + * pauth is "inactive", meaning all insns are implemented as
> + * a nop, or "active" when some action must be performed.
> + * The decision of which action to take is left to a helper.
> + */
> + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
> + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
> + }
> + }
> +
> + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
> + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
> + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
> + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
> + }
> + }
> +
> + return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
> +}
> +
> void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t *pflags)
> {
> @@ -11079,67 +11144,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> uint32_t flags = 0;
>
> if (is_a64(env)) {
> - ARMCPU *cpu = env_archcpu(env);
> - uint64_t sctlr;
> -
> *pc = env->pc;
> - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
> -
> - /* Get control bits for tagged addresses. */
> - {
> - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
> - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
> - int tbii, tbid;
> -
> - /* FIXME: ARMv8.1-VHE S2 translation regime. */
> - if (regime_el(env, stage1) < 2) {
> - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
> - tbid = (p1.tbi << 1) | p0.tbi;
> - tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
> - } else {
> - tbid = p0.tbi;
> - tbii = tbid & !p0.tbid;
> - }
> -
> - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
> - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
> - }
> -
> - if (cpu_isar_feature(aa64_sve, cpu)) {
> - int sve_el = sve_exception_el(env, current_el);
> - uint32_t zcr_len;
> -
> - /* If SVE is disabled, but FP is enabled,
> - * then the effective len is 0.
> - */
> - if (sve_el != 0 && fp_el == 0) {
> - zcr_len = 0;
> - } else {
> - zcr_len = sve_zcr_len_for_el(env, current_el);
> - }
> - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
> - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
> - }
> -
> - sctlr = arm_sctlr(env, current_el);
> -
> - if (cpu_isar_feature(aa64_pauth, cpu)) {
> - /*
> - * In order to save space in flags, we record only whether
> - * pauth is "inactive", meaning all insns are implemented as
> - * a nop, or "active" when some action must be performed.
> - * The decision of which action to take is left to a helper.
> - */
> - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
> - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
> - }
> - }
> -
> - if (cpu_isar_feature(aa64_bti, cpu)) {
> - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
> - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
> - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
> - }
> + flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx);
> + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
> flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
> }
> } else {
> @@ -11159,9 +11166,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> flags = FIELD_DP32(flags, TBFLAG_A32,
> XSCALE_CPAR, env->cp15.c15_cpar);
> }
> - }
>
> - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
> + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
> + }
>
> /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
> * states defined in the ARM ARM for software singlestep:
--
Alex Bennée
next prev parent reply other threads:[~2019-10-14 15:45 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-11 15:55 [PATCH v6 00/20] target/arm: Reduce overhead of cpu_get_tb_cpu_state Richard Henderson
2019-10-11 15:55 ` [PATCH v6 01/20] target/arm: Split out rebuild_hflags_common Richard Henderson
2019-10-11 15:55 ` [PATCH v6 02/20] target/arm: Split out rebuild_hflags_a64 Richard Henderson
2019-10-14 15:43 ` Alex Bennée [this message]
2019-10-11 15:55 ` [PATCH v6 03/20] target/arm: Split out rebuild_hflags_common_32 Richard Henderson
2019-10-14 15:53 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 04/20] target/arm: Split arm_cpu_data_is_big_endian Richard Henderson
2019-10-14 16:01 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 05/20] target/arm: Split out rebuild_hflags_m32 Richard Henderson
2019-10-14 16:13 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 06/20] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Richard Henderson
2019-10-14 16:17 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 07/20] target/arm: Split out rebuild_hflags_a32 Richard Henderson
2019-10-14 16:17 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 08/20] target/arm: Split out rebuild_hflags_aprofile Richard Henderson
2019-10-14 16:19 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 09/20] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Richard Henderson
2019-10-14 16:39 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 10/20] target/arm: Simplify set of PSTATE_SS " Richard Henderson
2019-10-14 18:21 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 11/20] target/arm: Hoist computation of TBFLAG_A32.VFPEN Richard Henderson
2019-10-14 18:46 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 12/20] target/arm: Add arm_rebuild_hflags Richard Henderson
2019-10-14 18:47 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 13/20] target/arm: Split out arm_mmu_idx_el Richard Henderson
2019-10-14 18:49 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 14/20] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Richard Henderson
2019-10-14 18:51 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 15/20] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Richard Henderson
2019-10-14 18:59 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 16/20] target/arm: Rebuild hflags at EL changes Richard Henderson
2019-10-14 19:01 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 17/20] target/arm: Rebuild hflags at MSR writes Richard Henderson
2019-10-14 19:03 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 18/20] target/arm: Rebuild hflags at CPSR writes Richard Henderson
2019-10-14 19:08 ` Alex Bennée
2019-10-14 19:15 ` Richard Henderson
2019-10-11 15:55 ` [PATCH v6 19/20] target/arm: Rebuild hflags for M-profile Richard Henderson
2019-10-14 19:08 ` Alex Bennée
2019-10-11 15:55 ` [PATCH v6 20/20] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Richard Henderson
2019-10-17 15:26 ` [PATCH v6 00/20] target/arm: Reduce overhead of cpu_get_tb_cpu_state Peter Maydell
2019-10-17 16:25 ` Richard Henderson
2019-10-17 17:01 ` Peter Maydell
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