From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47429) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fC8XB-0000qZ-AK for qemu-devel@nongnu.org; Fri, 27 Apr 2018 14:55:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fC8X8-0007JU-5a for qemu-devel@nongnu.org; Fri, 27 Apr 2018 14:55:53 -0400 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]:39754) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fC8X7-0007HD-Us for qemu-devel@nongnu.org; Fri, 27 Apr 2018 14:55:50 -0400 Received: by mail-wr0-x22c.google.com with SMTP id q3-v6so2682150wrj.6 for ; Fri, 27 Apr 2018 11:55:49 -0700 (PDT) References: <20180425012300.14698-1-richard.henderson@linaro.org> <87wowsk1ih.fsf@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <87wowsk1ih.fsf@linaro.org> Date: Fri, 27 Apr 2018 19:55:47 +0100 Message-ID: <87vaccjx70.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 0/9] target/arm: Fixups for ARM_FEATURE_V8_FP16 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org Alex Benn=C3=A9e writes: > Richard Henderson writes: > >> When running the gcc testsuite with current aarch64-linux-user, >> the testsuite detects the presence of the fp16 extension and >> enables lots of extra tests for builtins. >> >> Quite a few of these new tests fail because we missed implementing >> some instructions. We really should go back and verify that nothing >> else is missing from this (rather large) extension. > > So this set of instructions is generated from any ASL description that > contains "half": > > Failed 9 tests: > testcases.armv8.2_half/insn_FCCMP_H_floatccmp__INC.risu.bin > testcases.armv8.2_half/insn_FCCMPE_H_floatccmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMP_H_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMP_HZ_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMPE_H_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMPE_HZ_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCSEL_H_floatsel__INC.risu.bin Well that looks like a whole class of compares we are missing. I'll get to work on that. > testcases.armv8.2_half/insn_FMOV_H_floatimm__INC.risu.bin > testcases.armv8.2_half/insn_FSQRT_H_floatdp1__INC.risu.bin > > but I haven't checked to see if that is just instructions the FVP has in > full SVE mode that aren't in the just FP16 fixes branch I was testing > against. > > >> >> In addition, it tests some edge conditions on data that show flaws >> in the way we were performing integer<->fp conversion; particularly >> with respect to scaled conversion. >> >> >> r~ >> >> PS: FWIW, this was written against my tgt-arm-sve-9 tree, since I >> was trying to test sve as generated by gcc. I don't *think* there >> are any dependencies on any of the sve patches, but I didn't check. >> >> PPS: There are two more failures that might be qemu fp16 failures, >> but those are SIGSEGV. This patch set cures all of the SIGILL and >> (subsequent) SIGABRT type failures within the testsuite. >> >> >> Richard Henderson (9): >> target/arm: Implement vector shifted SCVF/UCVF for fp16 >> target/arm: Implement vector shifted FCVT for fp16 >> target/arm: Fix float16 to/from int16 >> target/arm: Clear SVE high bits for FMOV >> target/arm: Implement FMOV (general) for fp16 >> target/arm: Implement FCVT (scalar,integer) for fp16 >> target/arm: Implement FCVT (scalar,fixed-point) for fp16 >> target/arm: Implement FP data-processing (2 source) for fp16 >> target/arm: Implement FP data-processing (3 source) for fp16 >> >> target/arm/helper.h | 6 + >> target/arm/helper.c | 87 ++++++++++- >> target/arm/translate-a64.c | 371 +++++++++++++++++++++++++++++++++++++-= ------- >> 3 files changed, 399 insertions(+), 65 deletions(-) -- Alex Benn=C3=A9e