From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ute1x-00069q-8M for qemu-devel@nongnu.org; Mon, 01 Jul 2013 09:20:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ute1s-0000Gq-HJ for qemu-devel@nongnu.org; Mon, 01 Jul 2013 09:20:33 -0400 Received: from mail-gh0-f176.google.com ([209.85.160.176]:54153) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ute1s-0000GW-D4 for qemu-devel@nongnu.org; Mon, 01 Jul 2013 09:20:28 -0400 Received: by mail-gh0-f176.google.com with SMTP id z17so1956129ghb.7 for ; Mon, 01 Jul 2013 06:20:28 -0700 (PDT) From: Anthony Liguori In-Reply-To: <51D17E6B.9050503@redhat.com> References: <1372444009-11544-1-git-send-email-pbonzini@redhat.com> <1372444009-11544-5-git-send-email-pbonzini@redhat.com> <8761wy9ded.fsf@codemonkey.ws> <51D15830.5080504@redhat.com> <87li5q4epp.fsf@codemonkey.ws> <51D17E6B.9050503@redhat.com> Date: Mon, 01 Jul 2013 08:20:26 -0500 Message-ID: <87vc4uju1x.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 04/30] add a header file for atomic operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: qemu-devel@nongnu.org Paolo Bonzini writes: > Il 01/07/2013 15:00, Anthony Liguori ha scritto: >>> I >>> > cannot find the commit exactly, but I think mst added specific code for >>> > that. >> Right, I'm not questioning whether these functions have strong enough >> semantics in their implementation, but asking what their contract should >> be. >> >> Either we should document that these functions have atomic semantics or >> we should introduce another variant that guarantee atomic access. >> >> I think the later makes more sense since the majority of users probably >> don't need atomic semantics. > > I think many of these loads and stores do, actually; perhaps most. It > also matches what hardware does. Hrm, I'm not sure if that's true. PCI has an explicit LOCK# bit to enable exclusive access so my assumption would be that it doesn't by default. But either way, we should document the semantics. Regards, Anthony Liguori > > Paolo