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Thu, 22 Jun 2023 09:49:27 -0700 (PDT) References: <20230620175712.1331625-1-peter.maydell@linaro.org> <5b2bf86d-44fa-35ae-8049-b395d715adcb@linaro.org> <97cace68-b1d3-73f7-fa69-266ea0f36229@linaro.org> <780c8505-9cd7-87fd-c5cc-23f0e8aa455c@linaro.org> User-agent: mu4e 1.10.3; emacs 28.2 From: Thiago Jung Bauermann To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Richard Henderson , Peter Maydell , Alex =?utf-8?Q?Benn=C3=A9e?= , Thomas Huth , qemu-devel@nongnu.org Subject: Re: [PATCH] Revert "cputlb: Restrict SavedIOTLB to system emulation" In-reply-to: <780c8505-9cd7-87fd-c5cc-23f0e8aa455c@linaro.org> Date: Thu, 22 Jun 2023 18:49:26 +0200 Message-ID: <87wmzvh27d.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=thiago.bauermann@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello, Philippe Mathieu-Daud=C3=A9 writes: > On 21/6/23 11:39, Philippe Mathieu-Daud=C3=A9 wrote: >> On 21/6/23 07:19, Richard Henderson wrote: >>> On 6/20/23 19:57, Peter Maydell wrote: >>>> This manifests specifically in 'make check-tcg' failing, because code >>>> in cpus-common.c that sets up the CPUState::cpu_index field puts it >>>> at a different offset from the code in plugins/core.c in >>>> qemu_plugin_vcpu_init_hook() which reads the cpu_index field.=C2=A0 The >>>> latter then hits an assert because from its point of view every >>>> thread has a 0 cpu_index. There might be other weird behaviour too. >> Why isn't this covered by CI, and where could we add a such check? > > Actually it is covered and failed on staging: > https://gitlab.com/qemu-project/qemu/-/jobs/4503766933 Just for the record, it was also caught yesterday by the TCWG CI: https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-bisect/87/ --=20 Thiago