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From: Fabiano Rosas <farosas@suse.de>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 4/6] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward
Date: Fri, 24 Mar 2023 10:39:17 -0300	[thread overview]
Message-ID: <87wn36feuy.fsf@suse.de> (raw)
In-Reply-To: <20230323022237.1807512-4-npiggin@gmail.com>

Nicholas Piggin <npiggin@gmail.com> writes:

> This optional behavior was removed from the ISA in v3.0, see
> Summary of Changes preface:
>
>   Data Storage Interrupt Status Register for Alignment Interrupt:
>   Simplifies the Alignment interrupt by remov- ing the Data Storage
>   Interrupt Status Register (DSISR) from the set of registers modified
>   by the Alignment interrupt.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  target/ppc/excp_helper.c | 23 ++++++++++++++++-------
>  1 file changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 5f0e363363..c8b8eca3b1 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1456,13 +1456,22 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>          break;
>      }
>      case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
> -        /* Get rS/rD and rA from faulting opcode */
> -        /*
> -         * Note: the opcode fields will not be set properly for a
> -         * direct store load/store, but nobody cares as nobody
> -         * actually uses direct store segments.
> -         */
> -        env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> +        switch (env->excp_model) {

Slightly better would be to check on (env->insn_flags2 & PPC2_ISA300).
We were trying to phase out the usage of "exception models" wherever
possible in favor of specific feature/isa level flags.

> +        case POWERPC_EXCP_970:
> +        case POWERPC_EXCP_POWER7:
> +        case POWERPC_EXCP_POWER8:
> +            /* Get rS/rD and rA from faulting opcode */
> +            /*
> +             * Note: the opcode fields will not be set properly for a
> +             * direct store load/store, but nobody cares as nobody
> +             * actually uses direct store segments.
> +             */
> +            env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> +            break;
> +        default:
> +            /* Optional DSISR update was removed from ISA v3.0 */
> +            break;
> +        }
>          break;
>      case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
>          switch (env->error_code & ~0xF) {


  reply	other threads:[~2023-03-24 15:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-23  2:22 [PATCH 1/6] target/ppc: Fix width of some 32-bit SPRs Nicholas Piggin
2023-03-23  2:22 ` [PATCH 2/6] target/ppc: Better CTRL SPR implementation Nicholas Piggin
2023-03-23  2:22 ` [PATCH 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt Nicholas Piggin
2023-03-24 13:30   ` Fabiano Rosas
2023-03-27  4:25     ` Nicholas Piggin
2023-03-23  2:22 ` [PATCH 4/6] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward Nicholas Piggin
2023-03-24 13:39   ` Fabiano Rosas [this message]
2023-03-27  4:26     ` Nicholas Piggin
2023-03-23  2:22 ` [PATCH 5/6] target/ppc: Add SRR1 prefix indication to interrupt handlers Nicholas Piggin
2023-03-23  2:22 ` [PATCH 6/6] target/ppc: Implement HEIR SPR Nicholas Piggin
2023-05-09  9:51   ` Harsh Prateek Bora
2023-05-15  8:26     ` Nicholas Piggin
2023-05-15  8:32       ` Harsh Prateek Bora
2023-05-15  9:32         ` Harsh Prateek Bora
2023-05-15 10:45           ` Nicholas Piggin
2023-05-15 10:54             ` Harsh Prateek Bora

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