From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 25/40] target/arm: Update timer access for VHE
Date: Wed, 04 Dec 2019 18:35:13 +0000 [thread overview]
Message-ID: <87wobc6ise.fsf@linaro.org> (raw)
In-Reply-To: <20191203022937.1474-26-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++---------
> 1 file changed, 81 insertions(+), 21 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index a4a7f82661..023b8963cf 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2287,10 +2287,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
> * Writable only at the highest implemented exception level.
> */
> int el = arm_current_el(env);
> + uint64_t hcr;
> + uint32_t cntkctl;
>
> switch (el) {
> case 0:
> - if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
> + hcr = arm_hcr_el2_eff(env);
> + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
> + cntkctl = env->cp15.cnthctl_el2;
> + } else {
> + cntkctl = env->cp15.c14_cntkctl;
> + }
> + if (!extract32(cntkctl, 0, 2)) {
> return CP_ACCESS_TRAP;
> }
> break;
> @@ -2318,17 +2326,47 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
> {
> unsigned int cur_el = arm_current_el(env);
> bool secure = arm_is_secure(env);
> + uint64_t hcr = arm_hcr_el2_eff(env);
>
> - /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
> - if (cur_el == 0 &&
> - !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
> - return CP_ACCESS_TRAP;
> - }
> + switch (cur_el) {
> + case 0:
> + /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
> + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
> + return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
> + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
> + }
>
> - if (arm_feature(env, ARM_FEATURE_EL2) &&
> - timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
> - !extract32(env->cp15.cnthctl_el2, 0, 1)) {
> - return CP_ACCESS_TRAP_EL2;
> + /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
> + if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
> + return CP_ACCESS_TRAP;
> + }
> +
> + /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
> + if (hcr & HCR_E2H) {
> + if (timeridx == GTIMER_PHYS &&
> + !extract32(env->cp15.cnthctl_el2, 10, 1)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + } else {
> + /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
> + if (arm_feature(env, ARM_FEATURE_EL2) &&
> + timeridx == GTIMER_PHYS && !secure &&
> + !extract32(env->cp15.cnthctl_el2, 1, 1)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + }
> + break;
> +
> + case 1:
> + /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
> + if (arm_feature(env, ARM_FEATURE_EL2) &&
> + timeridx == GTIMER_PHYS && !secure &&
> + (hcr & HCR_E2H
> + ? !extract32(env->cp15.cnthctl_el2, 10, 1)
> + : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + break;
> }
> return CP_ACCESS_OK;
> }
> @@ -2338,19 +2376,41 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
> {
> unsigned int cur_el = arm_current_el(env);
> bool secure = arm_is_secure(env);
> + uint64_t hcr = arm_hcr_el2_eff(env);
>
> - /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
> - * EL0[PV]TEN is zero.
> - */
> - if (cur_el == 0 &&
> - !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
> - return CP_ACCESS_TRAP;
> - }
> + switch (cur_el) {
> + case 0:
> + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
> + /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
> + return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
> + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
> + }
>
> - if (arm_feature(env, ARM_FEATURE_EL2) &&
> - timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
> - !extract32(env->cp15.cnthctl_el2, 1, 1)) {
> - return CP_ACCESS_TRAP_EL2;
> + /*
> + * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
> + * EL0 if EL0[PV]TEN is zero.
> + */
> + if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
> + return CP_ACCESS_TRAP;
> + }
> + /* fall through */
> +
> + case 1:
> + if (arm_feature(env, ARM_FEATURE_EL2) &&
> + timeridx == GTIMER_PHYS && !secure) {
> + if (hcr & HCR_E2H) {
> + /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
> + if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + } else {
> + /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
> + if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + }
> + }
> + break;
> }
> return CP_ACCESS_OK;
> }
--
Alex Bennée
next prev parent reply other threads:[~2019-12-04 18:37 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 2:28 [PATCH v4 00/40] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-12-03 2:28 ` [PATCH v4 01/40] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-12-03 2:28 ` [PATCH v4 02/40] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-12-03 2:29 ` [PATCH v4 03/40] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-12-03 2:29 ` [PATCH v4 04/40] target/arm: Add TTBR1_EL2 Richard Henderson
2019-12-10 9:14 ` Laurent Desnogues
2019-12-03 2:29 ` [PATCH v4 05/40] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-12-03 2:29 ` [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-12-03 6:25 ` Philippe Mathieu-Daudé
2019-12-03 22:01 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 07/40] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-12-03 2:29 ` [PATCH v4 08/40] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2019-12-04 10:38 ` Alex Bennée
2019-12-06 15:45 ` Peter Maydell
2019-12-06 18:00 ` Richard Henderson
2019-12-06 18:01 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 09/40] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2019-12-04 10:40 ` Alex Bennée
2019-12-06 15:46 ` Peter Maydell
2019-12-06 18:05 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 10/40] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2019-12-04 11:00 ` Alex Bennée
2019-12-06 15:47 ` Peter Maydell
2019-12-06 18:20 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 11/40] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Richard Henderson
2019-12-04 11:01 ` Alex Bennée
2019-12-06 15:47 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2019-12-04 11:02 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2019-12-04 11:03 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 14/40] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2019-12-04 11:43 ` Alex Bennée
2019-12-04 14:27 ` Richard Henderson
2019-12-04 15:53 ` Alex Bennée
2019-12-04 16:19 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2019-12-04 11:48 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 16/40] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2019-12-04 11:56 ` Alex Bennée
2019-12-04 16:01 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2019-12-03 6:27 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 18/40] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-12-04 13:44 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 19/40] target/arm: Add regime_has_2_ranges Richard Henderson
2019-12-04 14:16 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 20/40] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-12-04 14:37 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 21/40] target/arm: Update arm_sctlr " Richard Henderson
2019-12-03 2:29 ` [PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2019-12-04 15:01 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 23/40] target/arm: Update ctr_el0_access " Richard Henderson
2019-12-04 16:11 ` Alex Bennée
2019-12-03 2:29 ` [PATCH v4 24/40] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-12-03 2:29 ` [PATCH v4 25/40] target/arm: Update timer access for VHE Richard Henderson
2019-12-04 18:35 ` Alex Bennée [this message]
2019-12-03 2:29 ` [PATCH v4 26/40] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2019-12-04 18:58 ` Alex Bennée
2019-12-04 19:47 ` Richard Henderson
2019-12-04 22:38 ` Alex Bennée
2019-12-05 15:09 ` Richard Henderson
2019-12-06 15:53 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-12-06 17:24 ` Peter Maydell
2019-12-06 18:36 ` Richard Henderson
2019-12-06 18:41 ` Peter Maydell
2019-12-06 18:53 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 28/40] target/arm: Add VHE timer " Richard Henderson
2019-12-06 17:33 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2019-12-06 17:05 ` Peter Maydell
2020-01-28 0:04 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 30/40] target/arm: Flush tlbs for E2&0 " Richard Henderson
2019-12-06 17:14 ` Peter Maydell
2020-01-29 17:05 ` Richard Henderson
2019-12-03 2:29 ` [PATCH v4 31/40] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-12-06 16:59 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 32/40] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2019-12-06 16:50 ` [PATCH v4 32/40] target/arm: Update {fp, sve}_exception_el " Peter Maydell
2019-12-03 2:29 ` [PATCH v4 33/40] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2019-12-06 16:08 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 34/40] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2019-12-06 16:46 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 35/40] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2019-12-06 16:03 ` Peter Maydell
2019-12-06 18:51 ` Richard Henderson
2019-12-06 19:15 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-12-06 15:57 ` Peter Maydell
2019-12-03 2:29 ` [PATCH v4 37/40] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2019-12-03 6:28 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 38/40] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2019-12-03 6:29 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 39/40] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2019-12-03 6:30 ` Philippe Mathieu-Daudé
2019-12-03 2:29 ` [PATCH v4 40/40] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2019-12-06 15:57 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87wobc6ise.fsf@linaro.org \
--to=alex.bennee@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).