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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Fri, 09 Mar 2018 15:15:36 +0000
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Subject: Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission
 v8.2
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To: Michael Clark <mjc@sifive.com>
Cc: Peter Maydell <peter.maydell@linaro.org>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@sifive.com>, QEMU Developers <qemu-devel@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org>


Michael Clark <mjc@sifive.com> writes:

<snip>
>
> BTW - I've integrated the following 3 branches into the riscv tree:
>
> - https://github.com/riscv/riscv-qemu/tree/softfloat-snan-abort-fix
> - https://github.com/riscv/riscv-qemu/tree/riscv-qemu-upstream-v8.2
> - https://github.com/michaeljclark/riscv-qemu/tree/qemu-devel
>
> into our `riscv-all` integration branch, and we're now passing all FPU
> tests, interestingly, including the NaN-boxing of single precision values
> into doubles. We'll need to check that the riscv-tests testsuite is
> exhastive enough... Suprised! I think Richard might have thought about
> our NaN-boxing
> issue or some other sort of magic is going on :-)
>
> - https://github.com/riscv/riscv-qemu/tree/riscv-all

Is the SNaN patch going to get re-posted now it has had a review?

--
Alex Benn=C3=A9e