From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41344) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVE21-0003e8-3i for qemu-devel@nongnu.org; Wed, 12 Jul 2017 05:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVE1y-0007X5-1w for qemu-devel@nongnu.org; Wed, 12 Jul 2017 05:34:05 -0400 Received: from mail-lf0-f42.google.com ([209.85.215.42]:32887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dVE1x-0007WR-Rn for qemu-devel@nongnu.org; Wed, 12 Jul 2017 05:34:02 -0400 Received: by mail-lf0-f42.google.com with SMTP id z78so11073533lff.0 for ; Wed, 12 Jul 2017 02:34:01 -0700 (PDT) References: <149942760788.8972.474351671751194003.stgit@frigg.lan> <149943205430.8972.17786409962934999706.stgit@frigg.lan> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <149943205430.8972.17786409962934999706.stgit@frigg.lan> Date: Wed, 12 Jul 2017 10:32:59 +0100 Message-ID: <87wp7e80fo.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v12 18/27] target/arm: [tcg, a64] Port to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?utf-8?Q?Llu=C3=ADs?= Vilanova Cc: qemu-devel@nongnu.org, "Emilio G. Cota" , Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Peter Maydell , "open list:ARM" Lluís Vilanova writes: > Incrementally paves the way towards using the generic instruction translation > loop. > > Signed-off-by: Lluís Vilanova > Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée > --- > target/arm/translate-a64.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 5c04ff3d8b..dc91661df0 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -11247,6 +11247,14 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, > init_tmp_a64_array(dc); > } > > +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) > +{ > + DisasContext *dc = container_of(dcbase, DisasContext, base); > + > + dc->insn_start_idx = tcg_op_buf_count(); > + tcg_gen_insn_start(dc->pc, 0, 0); > +} > + > void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, > TranslationBlock *tb) > { > @@ -11278,8 +11286,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, > > do { > dc->base.num_insns++; > - dc->insn_start_idx = tcg_op_buf_count(); > - tcg_gen_insn_start(dc->pc, 0, 0); > + aarch64_tr_insn_start(&dc->base, cs); > > if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { > CPUBreakpoint *bp; -- Alex Bennée